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Preliminary
HD66750/1
(128 x 128-dot Graphics LCD Controller/Driver with Four-grayscale Functions)
Rev 0.7 July 26th, 1999
Description
The HD66750/1, dot-matrix graphics LCD controller and driver LSI, displays 128-by-128-dot graphics for four monochrome grayscales. Since the HD66750/1 incorporates bit-operation functions and a 16-bit high-speed bus interface, it enables efficient data transfer and high-speed rewriting of data in the graphics RAM. The following functions allow the user to easily see a variety of information: a smooth scroll display function that fixed-displays a part of the graphics icons and perform vertical smooth scrolling of the remaining bit-map areas, a double-height display function, and a hardware-supported window cursor display function. The HD66750/1 has various functions to reduce the power consumption of an LCD system such as lowvoltage operation of 1.8 V min., a booster to generate maximum seven-times LCD drive voltage from the supplied voltage, and voltage-followers to decrease the direct current flow in the LCD drive bleederresistors. Combining these hardware functions with software functions, such as a partial display with low-duty drive and standby and sleep modes, allows precise power control. The HD66750/1 is suitable for any mid-sized or small portable battery-driven product requiring long-term driving capabilities, such as digital cellular phones supporting a WWW browser, bidirectional pagers, and small PDAs.
Features
128 128-dot graphics display LCD controller/driver for four monochrome grayscales Fixed display of graphics icons (pictograms) 16-/8-bit high-speed bus interface capability Bit-operation functions for graphics processing incorporated: N Write-data mask function in bit units N Bit rotation function N Bit logic-operation function Low-power operation support: N Vcc = 1.8 to 3.6 V (low voltage) N VLCD = 5 to 15.5 V (liquid crystal drive voltage) N Two-, five-, six-, or seven-times booster for liquid crystal drive voltage N 64-step contrast adjuster and voltage followers to decrease direct current flow in the LCD drive bleeder-resistors
1
HD66750/1
N Power-save functions such as the standby mode and sleep mode supported N Programmable drive duty ratios and bias values displayed on LCD 128-segment 128-common liquid crystal display driver n-raster-row AC liquid-crystal drive (C-pattern waveform drive) Duty ratio and drive bias (selectable by program) Window cursor display supported by hardware Vertical smooth scroll Partial smooth scroll control (fixed display of graphics icons) Vertical double-height display by each display raster-row Black-and-white reversed display No wait time for instruction execution and RAM access Internal oscillation and hardware reset Shift change of segment and common driver

Table 1
Progammable Display Sizes and Duty Ratios
Graphics Display
Duty Optimum Bit-map 12 x 12-dot Ratio Drive Bias Display Area Font Width 1/16 1/24 1/32 1/72 1/80 1/88 1/96 1/5 1/6 1/6 1/9 1/10 1/10 1/10 128 x 16 dots 1 line x 10 characters 128 x 24 dots 2 lines x 10 characters 128 x 32 dots 2 lines x 10 characters 128 x 72 dots 6 lines x 10 characters 128 x 80 dots 6 lines x 10 characters 128 x 88 dots 7 lines x 10 characters 128 x 96 dots 8 lines x 10 characters 128 x 104 dots 128 x 112 dots 128 x 120 dots 128 x 128 dots 8 lines x 10 characters 9 lines x 10 characters
12 x 13-dot 14 x 15-dot Font Width Font Width 1 line x 10 characters 1 line x 10 characters 1 line x 9 characters 1 line x 9 characters
16 x 16-dot Font Width 1 line x 8 characters 1 line x 8 characters 2 lines x 8 characters 4 lines x 8 characters 5 lines x 8 characters 5 lines x 8 characters 6 lines x 8 characters 6 lines x 8 characters 7 lines x 8 characters 7 lines x 8 characters 8 lines x 8 characters
8 x 10-dot Font Width 1 line x 16 characters 2 lines x 16 characters 3 lines x 16 characters 7 lines x 16 characters 8 lines x 16 characters 8 lines x 16 characters 9 lines x 16 characters 10 lines x 16 characters 11 lines x 16 characters 12 lines x 16 characters 12 lines x 16 characters
2 lines x 10 2 lines x 9 characters characters 5 lines x 10 4 lines x 9 characters characters 6 lines x 10 5 lines x 9 characters characters 6 lines x 10 5 lines x 9 characters characters 7 lines x 10 6 lines x 9 characters characters 8 lines x 10 6 lines x 9 characters characters 8 lines x 10 7 lines x 9 characters characters
1/104 1/11 1/112 1/11 1/120 1/11 1/128 1/11
10 lines x 10 9 lines x 10 8 lines x 9 characters characters characters 10 lines x 10 9 lines x 10 8 lines x 9 characters characters characters
2
HD66750/1
Total Current Consumption Characteristics (Vcc = 3 V, TYP Conditions, LCD Drive Power Current Included)
Total Power Consumption Normal Display Operation Character Display Dot Size Duty Ratio R-C Oscillation Frame Frequency Frequency 70 kHz 70 kHz 70 kHz 70 kHz 70 kHz 70 kHz 70 kHz 70 kHz 70 kHz 70 kHz 70 kHz 72 Hz 72 Hz 72 Hz 71 Hz 73 Hz 74 Hz 74 Hz 73 Hz 71 Hz 76 Hz 72 Hz Internal Logic (15 mA) (15 mA) (15 mA) (40 mA) (40 mA) (45 mA) (45 mA) (45 mA) (50 mA) (50 mA) (50 mA) LCD Power (15 mA) (15 mA) (15 mA) (18 mA) (18 mA) (18 mA) (20 mA) (20 mA) (25 mA) (25 mA) (25 mA) Sleep Mode Standby Mode
Total*
128 x 16 dots 1/16 128 x 24 dots 1/24 128 x 32 dots 1/32 128 x 72 dots 1/72 128 x 80 dots 1/80 128 x 88 dots 1/88 128 x 96 dots 1/96 128 x 104 dots 1/104 128 x 112 dots 1/112 128 x 120 dots 1/120 128 x 128 dots 1/128
Two-times (10 mA) 0.1 mA (45 mA) Two-times (10 mA) (45 mA) Two-times (10 mA) (45 mA) Five-times (10 mA) (130 mA) Five-times (10 mA) (130 mA) Five-times (10 mA) (135 mA) Five-times (10 mA) (145 mA) Five-times (10 mA) (145 mA) Six-times (200 mA) Six-times (200 mA) Six-times (200 mA) (10 mA) (10 mA) (10 mA)
Note: When a two-, five-, six-, or seven-times booster is used: the total power consumption = internal logic current + LCD power current x 2 (two-times booster), the total power consumption = internal logic current + LCD power current x 5 (five-times booster), the total power consumption = internal logic current + LCD power current x 6 (six-times booster), and the total power consumption = internal logic current + LCD power current x 7 (seven-times booster)
Type Name
Types HD66750TB0 HCD66750BP HD66751TB0 HCD66751BP External Dimensions Bending TCP Au-bump chip Bending TCP Au-bump chip One side of COM (Output from one side of the chip) COM Driver Arrangement Both sides of COM (Output from left and right sides of the chip) Display Four monochrome grayscales
3
HD66750/1
LCD Family Comparison
Items Character display sizes Graphic display sizes Grayscale display Multiplexing icons Annunciator Key scan control LED control ports General output ports Operating power voltages Liquid crystal drive voltages Serial bus Parallel bus Liquid crystal drive duty ratios Liquid crystal drive biases Liquid crystal drive waveforms Liquid crystal voltage booster Bleeder-resistor for liquid crystal drive Liquid crystal drive operational amplifier Liquid crystal contrast adjuster Horizontal smooth scroll Vertical smooth scroll Double-height display DDRAM CGROM CGRAM SEGRAM No. of CGROM fonts No. of CGRAM fonts Font sizes Bit map area R-C oscillation resistor/ oscillation frequency Reset function Low power control HD66705U 12 characters x 2 lines N N 40 Static: 10 N N N 2.4 V to 5.5 V 3 V to 9 V Clock-synchronized serial 4 bits, 8 bits 1/10, 18 1/4 B Two- or three-times Incorporated (external) Incorporated Incorporated N Line unit Yes 60 x 8 9,600 32 x 5 8 x5 240 4 5 x8 N External resistor (40, 80 kHz) External Partial display off, Oscillation off, Liquid crystal power off SEG only N N TCP-153 Yes Yes 153 9.69 x 2.73 120 mm HD66717 12 characters x 4 lines N N 40 Static: 10 N N N 2.4 V to 5.5 V 3 V to 13 V I2C, Clock-synchronized serial 4 bits, 8 bits 1/10, 18, 26, 34 1/4, 1/6 B Two- or three-times Incorporated (external) Incorporated Incorporated N Line unit Yes 60 x 8 9,600 32 x 5 8 x5 240 4 5 x8 N External resistor (40-160 kHz) External Partial display off, Oscillation off, Liquid crystal power off SEG only N N TCP-153 Yes Yes 153 10.88 x 2.89 120 mm HD66727 12 characters x 4 lines N N 40 Static: 12 4 x8 3 3 2.4 V to 5.5 V 3 V to 13 V I2C, Clock-synchronized serial N 1/10, 18, 26, 34 1/4, 1/6 B Two- or three-times Incorporated (external) Incorporated Incorporated N Line unit Yes 60 x 8 11,520 32 x 6 8 x6 240 4 5 x 8, 6 x 8 N External resistor (40-160 kHz) External Partial display off, Oscillation off, Liquid crystal power off, Key wake-up interrupt SEG, COM N N TCP-158 Yes Yes 158 11.39 x 2.89 120 mm
SEG/COM direction switching QFP package TQFP package TCP package Bare chip Bumped chip No. of pins Chip sizes Pad intervals
4
HD66750/1
LCD Family Comparison (cont)
Items Character display sizes Graphic display sizes Grayscale display Multiplexing icons Annunciator Key scan control LED control ports General output ports Operating power voltages Liquid crystal drive voltages Serial bus Parallel bus Liquid crystal drive duty ratios Liquid crystal drive biases Liquid crystal drive waveforms Liquid crystal voltage booster Bleeder-resistor for liquid crystal drive Liquid crystal drive operational amplifier Liquid crystal contrast adjuster Horizontal smooth scroll Vertical smooth scroll Double-height display DDRAM CGROM CGRAM SEGRAM No. of CGROM fonts No. of CGRAM fonts Font sizes Bit map areas R-C oscillation resistor/ oscillation frequency Reset function Low power control HD66724 12 characters x 3 lines 72 x 26 dots N 144 1/2 duty: 144 8 x4 N 3 1.8 V to 5.5 V 3 V to 6.5 V Clock-synchronized serial 4 bits, 8 bits 1/2, 10, 18, 26 1/4 to 1/6.5 B Single, two-, or three-times Incorporated (external) Incorporated Incorporated 3-dot unit Line unit Yes 80 x 8 20,736 384 x 8 72 x 8 240 + 192 64 6 x8 72 x 26 HD66725 16 characters x 3 lines 96 x 26 dots N 192 1/2 duty: 192 8 x4 N 3 1.8 V to 5.5 V 3 V to 6.5 V Clock-synchronized serial 4 bits, 8 bits 1/2, 10, 18, 26 1/4 to 1/6.5 B Single, two-, or three-times Incorporated (external) Incorporated Incorporated 3-dot unit Line unit Yes 80 x 8 20,736 384 x 8 96 x 8 240 + 192 64 6 x8 96 x 26 HD66726 16 characters x 5 lines 96 x 42 dots N 192 1/2 duty: 192 8 x4 N 3 1.8 V to 5.5 V 4.5 V to 11 V Clock-synchronized serial 4 bits, 8 bits 1/2, 10, 18, 26, 34, 42 1/2 to 1/8 B Single, two-, three-, or fourtimes Incorporated (external) Incorporated Incorporated N Line unit Yes 80 x 8 20,736 480 x 8 96 x 8 240 + 192 64 6 x8 96 x 42
External resistor, incorporated External resistor, incorporated External resistor (32 kHz) (32 kHz) (50 kHz) External Partial display off, Oscillation off, Liquid crystal power off, Key wake-up interrupt SEG, COM N N TCP-146 N Yes 146 10.34 x 2.51 80 mm External Partial display off, Oscillation off, Liquid crystal power off, Key wake-up interrupt SEG, COM N N TCP-170 N Yes 170 10.97 x 2.51 80 mm External Partial display off, Oscillation off, Liquid crystal power off, Key wake-up interrupt SEG, COM N N TCP-188 Yes Yes 188 13.13 x 2.51 100 mm
SEG/COM direction switching QFP package TQFP package TCP package Bare chip Bumped chip No. of pins Chip sizes Pad intervals
5
HD66750/1
LCD Family Comparison (cont)
(WS available) Items Character display sizes Graphic display sizes Grayscale display Multiplexing icons Annunciator Key scan control LED control ports General output ports Operating power voltages Liquid crystal drive voltages Serial bus Parallel bus Liquid crystal drive duty ratios Liquid crystal drive biases Liquid crystal drive waveforms Liquid crystal voltage booster Bleeder-resistor for liquid crystal drive Liquid crystal drive operational amplifier Liquid crystal contrast adjuster Horizontal smooth scroll Vertical smooth scroll Double-height display DDRAM CGROM CGRAM SEGRAM No. of CGROM fonts No. of CGRAM fonts Font sizes Bit map areas R-C oscillation resistor/ oscillation frequency Reset function Low power control HD66728 16 characters x 10 lines 112 x 80 dots N N N 8 x4 N 3 1.8 V to 5.5 V 4.5 V to 15 V Clock-synchronized serial 4 bits, 8 bits HD66729 N 105 x 68 dots N N N N N N 1.8 V to 5.5 V 4.0 V to 13 V Clock-synchronized serial 4 bits, 8 bits
1/8, 16, 24, 32, 40, 48, 56, 64, 1/8, 16, 24, 32, 40, 48, 56, 64, 72, 80 68 1/4 to 1/10 B, C Three-, four-, or five-times Incorporated (external) Incorporated Incorporated N Line unit Yes 160 x 8 20,736 1,120 x 8 N 240 + 192 64 6 x8 112 x 80 External resistor (7090 kHz) External Partial display off, Oscillation off, Liquid crystal power off, Key wake-up interrupt SEG, COM N N TCP-243 N Yes 243 13.67 x 2.78 70 mm 1/4 to 1/9 B, C Two-, three-, four-, or fivetimes Incorporated (external) Incorporated Incorporated N Line unit Yes N N 1,050 x 8 N N N N 105 x 68 External resistor (75 kHz) External Partial display off, Oscillation off, Liquid crystal power off SEG, COM N N TCP-213 N Yes 213 12.23 x 2.52 70 mm
SEG/COM direction switching QFP package TQFP package TCP package Bare chip Bumped chip No. of pins Chip sizes Pad intervals
6
HD66750/1
LCD Family Comparison (cont)
(Under development) Items Character display sizes Graphic display sizes Grayscale display Multiplexing icons Annunciator Key scan control LED control ports General output ports Operating power voltages Liquid crystal drive voltages Serial bus Parallel bus Liquid crystal drive duty ratios Liquid crystal drive biases Liquid crystal drive waveforms Liquid crystal voltage booster Bleeder-resistor for liquid crystal drive Liquid crystal drive operational amplifier Liquid crystal contrast adjuster Horizontal smooth scroll Vertical smooth scroll Double-height display DDRAM CGROM CGRAM SEGRAM No. of CGROM fonts No. of CGRAM fonts Font sizes Bit map areas R-C oscillation resistor/ oscillation frequency Reset function Low power control HD66741 N 128 x 80 dots N N N N N 3 1.8 V to 5.5 V 4.5 V to 15 V Clock-synchronized serial 4 bits, 8 bits HD66750/751 N 128 x 128 dots Four monochrome grayscales N N N N N 1.8 V to 3.6 V 5 V to 15.5 V N 8 bits, 16 bits
1/8, 16, 24, 32, 40, 48, 56, 64, 1/16, 24, 72, 80, 88, 96, 104, 72, 80 112, 120, 128 1/4 to 1/10 B, C Three-, four-, or five-times Incorporated (external) Incorporated Incorporated N Line unit Yes N N 1,280 x 8 N N N N 128 x 80 External resistor (7090 kHz) External Partial display off, Oscillation off, Liquid crystal power off SEG, COM N N TCP-254 N Yes 243 14.30 x 2.78 70 mm 1/4 to 1/11 B, C Two-, five-, six-, or seven-times Incorporated (external) Incorporated Incorporated N Line unit Yes N N 4,096 x 8 N N N N 128 x 128 External resistor (70 kHz) External Partial display off, Oscillation off, Liquid crystal power off SEG, COM N N TCP-308 N Yes 308 10.97 x 4.13 60 mm
SEG/COM direction switching QFP package TQFP package TCP package Bare chip Bumped chip No. of pins Chip sizes Pad intervals
7
HD66750/1
HD66750/1 Block Diagram
OSC1 OSC2
RESET* TEST
CPG
Timing generator Instruction register (IR) Instruction decoder
16 IM1-0
Address counter (AC)
128-bit bidirectional common shift register
Common driver
COM1/128 COM128/1
CS* RS E/WR* RW/RD* 16 DB0-DB15 System interface 16-bit bus 8-bit bus
16
Bit operation
16 16 12 Read data latch 16 16 128-bit latch circuit Segment driver
SEG1/128SEG128/1
Vci C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5C6+ C6VLOUT Graphic RAM (CGRAM) 4,096 bytes Two-, five-, six-, and seven-times booster
LCD drive voltage selector
Four grayscale control circuit
Window cursor control
Contrast adjuster Vcc
Drive bias controller
VTEST VR VLCD OPOFF
+R
+R
+R0
+R
+R
V1OUT
V2OUT
V3OUT
V4OUT
V5OUT
GND
8
HD66750/1
HD66750 Pad Arrangement
COM104/25 COM103/26 COM102/27 COM101/28 COM100/29 COM99/30 COM98/31 COM97/32 COM96/33 COM95/34 COM94/35 COM93/36 COM92/37 COM91/38 COM90/39 COM89/40 COM88/41 COM87/42 COM86/43 COM85/44 COM84/45 COM83/46 COM82/47 COM81/48 COM80/49 COM79/50 COM78/51 COM77/52 COM76/53 COM75/54 COM74/55 COM73/56 COM72/57 COM71/58 COM70/59 COM69/60 COM68/61 COM67/62 COM66/63 COM65/64 COM16/113 COM15/114 COM14/115 COM13/116 COM12/117 COM11/118 COM10/119 COM9/120 COM8/121 COM7/122 COM6/123 COM5/124 COM4/125 COM3/126 COM2/127 COM1/128
Dummy1
Dummy48 Dummy47 Dummy46 Dummy45 Dummy44 Dummy43 Dummy42 Dummy41 Dummy40 Dummy39 Dummy38 Dummy37 Dummy36 COM105/24 COM106/23 COM107/22 COM108/21 COM109/20 COM110/19 COM111/18 COM112/17 SEG128/1 SEG127/2 SEG126/3 SEG125/4 SEG124/5 SEG123/6 SEG122/7 SEG121/8 SEG120/9 SEG119/10 SEG118/11 SEG117/12 SEG116/13 SEG115/14 SEG114/15 SEG113/16 SEG112/17 SEG111/18 SEG110/19 SEG109/20 SEG108/21 SEG107/22 SEG106/23 SEG105/24 SEG104/25 SEG103/26 SEG102/27 SEG101/28 SEG100/29 SEG99/30 SEG98/31 SEG97/32 SEG96/33 SEG95/34 SEG94/35 SEG93/36 SEG92/37 SEG91/38 SEG90/39 SEG89/40 SEG88/41 SEG87/42 SEG86/43 SEG85/44 SEG84/45 SEG83/46 SEG82/47 SEG81/48 SEG80/49 SEG79/50 SEG78/51 SEG77/52 SEG76/53 SEG75/54 SEG74/55 SEG73/56 SEG72/57 SEG71/58 SEG70/59 SEG69/60 SEG68/61 SEG67/62 SEG66/63 SEG65/64 SEG64/65 SEG63/66 SEG62/67 SEG61/68 SEG60/69 SEG59/70 SEG58/71 SEG57/72 SEG56/73 SEG55/74 SEG54/75 SEG53/76 SEG52/77 SEG51/78 SEG50/79 SEG49/80 SEG48/81 SEG47/82 SEG46/83 SEG45/84 SEG44/85 SEG43/86 SEG42/87 SEG41/88 SEG40/89 SEG39/90 SEG38/91 SEG37/92 SEG36/93 SEG35/94 SEG34/95 SEG33/96 SEG32/97 SEG31/98 SEG30/99 SEG29/100 SEG28/101 SEG27/102 SEG26/103 SEG25/104 SEG24/105 SEG23/106 SEG22/107 SEG21/108 SEG20/109 SEG19/110 SEG18/111 SEG17/112 SEG16/113 SEG15/114 SEG14/115 SEG13/116 SEG12/117 SEG11/118 SEG10/119 SEG9/120 SEG8/121 SEG7/122 SEG6/123 SEG5/124 SEG4/125 SEG3/126 SEG2/127 SEG1/128 COM128/1 COM127/2 COM126/3 COM125/4 COM124/5 COM123/6 COM122/7 COM121/8 Dummy35 Dummy34 Dummy33 Dummy32 Dummy31 Dummy30 Dummy29 Dummy28 Dummy27 Dummy26 Dummy25 Dummy24 Dummy23 COM120/9 COM119/10 COM118/11 COM117/12 COM116/13 COM115/14 COM114/15 COM113/16 COM64/65 COM63/66 COM62/67 COM61/68 COM60/69 COM59/70 COM58/71 COM57/72 COM56/73 COM55/74 COM54/75 COM53/76 COM52/77 COM51/78 COM50/79 COM49/80 COM48/81 COM47/82 COM46/83 COM45/84 COM44/85 COM43/86 COM42/87 COM41/88 COM40/89 COM39/90 COM38/91 COM37/92 COM36/93 COM35/94 COM34/95 COM33/96 COM32/97 COM31/98 COM30/99 COM29/100 COM28/101 COM27/102 COM26/103 COM25/104 COM24/105 COM23/106 COM22/107 COM21/108 COM20/109 COM19/110 COM18/111 COM17/112
Chip size: 10.97 mm X 4.13 mm Pad coordinates: Pad center Coordinate origin: Chip center Au bump size: 40 m x 90 m Chip corner bump size : 90 m x 90 m
(Dummy1, Dummy22, Dummy23 and Dummy 48)
Au bump pitch: 60 m (min.) Au bump height: 20 m (typ.)
Dummy2 Dummy3 Dummy4 Dummy5 Dummy6 Dummy7 Dummy8 Dummy9 Dummy10 GNDDUM1 IM1 IM1 IM0 IM0 VccDUM1 OPOFF OPOFF TEST TEST GNDDUM2 DB15 DB15 DB14 DB14 DB13 DB13 DB12 DB12 DB11 DB11 DB10 DB10 DB9 DB9 DB8 DB8 DB7 DB7 DB6 DB6 DB5 DB5 DB4 DB4 DB3 DB3 DB2 DB2 DB1 DB1 DB0 DB0 GNDDUM3 RESET* RESET* CS* CS* RS RS E/WR* E/WR* RW/RD* RW/RD* GND GND GND GND GND GND GND GND GND OSC2 OSC2 OSC1 OSC1 Vcc Vcc Vci Vci C6+ C6+ C6C6C5+ C5+ C5C5C4+ C4+ C4C4C3+ C3+ C3C3C2+ C2+ C2C2C1+ C1+ C1C1VLOUT VLOUT VLCD VLCD V1OUT V2OUT V3OUT V4OUT V5OUT VTEST Dummy11 Dummy12 Dummy13 Dummy14 Dummy15 Dummy16 Dummy17 Dummy18 Dummy19 Dummy20 Dummy21 Dummy22
HD66750
(Top view)
Y
X
(note) This figure is shown pad arrangement from chip top view which has Au-bumps and LSI pattern layer.
HITACHI
9
HD66750/1
HD66751 Pad Arrangement
SEG73/56 SEG74/55 SEG75/54 SEG76/53 SEG77/52 SEG78/51 SEG79/50 SEG80/49 SEG81/48 SEG82/47 SEG83/46 SEG84/45 SEG85/44 SEG86/43 SEG87/42 SEG88/41 SEG89/40 SEG90/39 SEG91/38 SEG92/37 SEG93/36 SEG94/35 SEG95/34 SEG96/33 SEG97/32 SEG98/31 SEG99/30 SEG100/29 SEG101/28 SEG102/27 SEG103/26 SEG104/25 SEG105/24 SEG106/23 SEG107/22 SEG108/21 SEG109/20 SEG110/19 SEG111/18 SEG112/17 SEG113/16 SEG114/15 SEG115/14 SEG116/13 SEG117/12 SEG118/11 SEG119/10 SEG120/9 SEG121/8 SEG122/7 SEG123/6 SEG124/5 SEG125/4 SEG126/3 SEG127/2 SEG128/1 Dummy48 Dummy47 Dummy46 Dummy45 Dummy44 Dummy43 Dummy42 Dummy41 Dummy40 Dummy39 Dummy38 Dummy37 Dummy36 SEG72/57 SEG71/58 SEG70/59 SEG69/60 SEG68/61 SEG67/62 SEG66/63 SEG65/64 SEG64/65 SEG63/66 SEG62/67 SEG61/68 SEG60/69 SEG59/70 SEG58/71 SEG57/72 SEG56/73 SEG55/74 SEG54/75 SEG53/76 SEG52/77 SEG51/78 SEG50/79 SEG49/80 SEG48/81 SEG47/82 SEG46/83 SEG45/84 SEG44/85 SEG43/86 SEG42/87 SEG41/88 SEG40/89 SEG39/90 SEG38/91 SEG37/92 SEG36/93 SEG35/94 SEG34/95 SEG33/96 SEG32/97 SEG31/98 SEG30/99 SEG29/100 SEG28/101 SEG27/102 SEG26/103 SEG25/104 SEG24/105 SEG23/106 SEG22/107 SEG21/108 SEG20/109 SEG19/110 SEG18/111 SEG17/112 SEG16/113 SEG15/114 SEG14/115 SEG13/116 SEG12/117 SEG11/118 SEG10/119 SEG9/120 SEG8/121 SEG7/122 SEG6/123 SEG5/124 SEG4/125 SEG3/126 SEG2/127 SEG1/128 COM128/1 COM127/2 COM126/3 COM125/4 COM124/5 COM123/6 COM122/7 COM121/8 COM120/9 COM119/10 COM118/11 COM117/12 COM116/13 COM115/14 COM114/15 COM113/16 COM112/17 COM111/18 COM110/19 COM109/20 COM108/21 COM107/22 COM106/23 COM105/24 COM104/25 COM103/26 COM102/27 COM101/28 COM100/29 COM99/30 COM98/31 COM97/32 COM96/33 COM95/34 COM94/35 COM93/36 COM92/37 COM91/38 COM90/39 COM89/40 COM88/41 COM87/42 COM86/43 COM85/44 COM84/45 COM83/46 COM82/47 COM81/48 COM80/49 COM79/50 COM78/51 COM77/52 COM76/53 COM75/54 COM74/55 COM73/56 COM72/57 COM71/58 COM70/59 COM69/60 COM68/61 COM67/62 COM66/63 COM65/64 COM64/65 COM63/66 COM62/67 COM61/68 COM60/69 COM59/70 COM58/71 COM57/72 Dummy35 Dummy34 Dummy33 Dummy32 Dummy31 Dummy30 Dummy29 Dummy28 Dummy27 Dummy26 Dummy25 Dummy24 Dummy23 COM56/73 COM55/74 COM54/75 COM53/76 COM52/77 COM51/78 COM50/79 COM49/80 COM48/81 COM47/82 COM46/83 COM45/84 COM44/85 COM43/86 COM42/87 COM41/88 COM40/89 COM39/90 COM38/91 COM37/92 COM36/93 COM35/94 COM34/95 COM33/96 COM32/97 COM31/98 COM30/99 COM29/100 COM28/101 COM27/102 COM26/103 COM25/104 COM24/105 COM23/106 COM22/107 COM21/108 COM20/109 COM19/110 COM18/111 COM17/112 COM16/113 COM15/114 COM14/115 COM13/116 COM12/117 COM11/118 COM10/119 COM9/120 COM8/121 COM7/122 COM6/123 COM5/124 COM4/125 COM3/126 COM2/127 COM1/128
Chip size: 10.97 mm X 4.13 mm Pad coordinates: Pad center Coordinate origin: Chip center Au bump size: 40 m x 90 m Chip corner bump size : 90 m x 90 m
(Dummy1, Dummy22, Dummy23 and Dummy 48)
Dummy1 Dummy2 Dummy3 Dummy4 Dummy5 Dummy6 Dummy7 Dummy8 Dummy9 Dummy10 GNDDUM1 IM1 IM1 IM0 IM0 VccDUM1 OPOFF OPOFF TEST TEST GNDDUM2 DB15 DB15 DB14 DB14 DB13 DB13 DB12 DB12 DB11 DB11 DB10 DB10 DB9 DB9 DB8 DB8 DB7 DB7 DB6 DB6 DB5 DB5 DB4 DB4 DB3 DB3 DB2 DB2 DB1 DB1 DB0 DB0 GNDDUM3 RESET* RESET* CS* CS* RS RS E/WR* E/WR* RW/RD* RW/RD* GND GND GND GND GND GND GND GND GND OSC2 OSC2 OSC1 OSC1 Vcc Vcc Vci Vci C6+ C6+ C6C6C5+ C5+ C5C5C4+ C4+ C4C4C3+ C3+ C3C3C2+ C2+ C2C2C1+ C1+ C1C1VLOUT VLOUT VLCD VLCD V1OUT V2OUT V3OUT V4OUT V5OUT VTEST Dummy11 Dummy12 Dummy13 Dummy14 Dummy15 Dummy16 Dummy17 Dummy18 Dummy19 Dummy20 Dummy21 Dummy22
Au bump pitch: 60 m (min.) Au bump height: 20 m (typ.)
HD66751
(Top view)
Y
X
(note) This figure is shown pad arrangement from chip top view which has Au-bumps and LSI pattern layer.
HITACHI
10
HD66750/1 HD66750 Pad Coordinate
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 PAD NAME Dummy1 Dummy2 Dummy3 Dummy4 Dummy5 Dummy6 Dummy7 Dummy8 Dummy9 Dummy10 GNDDUM1 IM1 IM1 IM0 IM0 VccDUM1 OPOFF OPOFF TEST TEST GNDDUM2 DB15 DB15 DB14 DB14 DB13 DB13 DB12 DB12 DB11 DB11 DB10 DB10 DB9 DB9 DB8 DB8 DB7 DB7 DB6 DB6 DB5 DB5 DB4 DB4 DB3 DB3 DB2 DB2 DB1 DB1 DB0 DB0 GNDDUM3 RESET* RESET* CS* CS* RS RS E/WR* E/WR* RW/RD* RW/RD* GND GND GND GND GND GND GND GND GND OSC2 OSC2 OSC1 OSC1 Vcc Vcc Vci Vci C6+ X -5269 -5089 -5029 -4969 -4909 -4848 -4788 -4728 -4668 -4608 -4454 -4394 -4334 -4210 -4150 -4086 -4026 -3966 -3842 -3782 -3722 -3658 -3598 -3474 -3414 -3290 -3230 -3106 -3046 -2922 -2862 -2738 -2678 -2554 -2494 -2370 -2310 -2186 -2126 -2002 -1942 -1818 -1758 -1634 -1574 -1450 -1390 -1266 -1206 -1083 -1022 -899 -838 -775 -715 -654 -531 -471 -347 -287 -163 -103 21 81 151 211 271 332 392 452 512 572 632 702 762 886 946 1119 1179 1342 1402 1522 Y -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1849 -1849 -1849 -1849 -1849 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 PAD NAME C6+ C6C6C5+ C5+ C5C5C4+ C4+ C4C4C3+ C3+ C3C3C2+ C2+ C2C2C1+ C1+ C1C1VLOUT VLOUT VLCD VLCD V1OUT V2OUT V3OUT V4OUT V5OUT VTEST Dummy11 Dummy12 Dummy13 Dummy14 Dummy15 Dummy16 Dummy17 Dummy18 Dummy19 Dummy20 Dummy21 Dummy22 COM17/112 COM18/111 COM19/110 COM20/109 COM21/108 COM22/107 COM23/106 COM24/105 COM25/104 COM26/103 COM27/102 COM28/101 COM29/100 COM30/99 COM31/98 COM32/97 COM33/96 COM34/95 COM35/94 COM36/93 COM37/92 COM38/91 COM39/90 COM40/89 COM41/88 COM42/87 COM43/86 COM44/85 COM45/84 COM46/83 COM47/82 COM48/81 COM49/80 COM50/79 COM51/78 COM52/77 COM53/76 X 1582 1703 1763 1883 1943 2063 2124 2244 2304 2424 2484 2605 2665 2785 2845 2965 3025 3146 3206 3326 3386 3506 3566 3687 3747 3867 3927 4047 4108 4168 4228 4288 4348 4488 4548 4608 4668 4728 4788 4848 4909 4969 5029 5089 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 Y -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1653 -1593 -1533 -1473 -1413 -1353 -1293 -1232 -1172 -1112 -1052 -992 -932 -872 -812 -752 -691 -631 -571 -511 -451 -391 -331 -271 -210 -150 -90 -30 30 90 150 210 271 331 391 451 511 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 PAD NAME COM54/75 COM55/74 COM56/73 COM57/72 COM58/71 COM59/70 COM60/69 COM61/68 COM62/67 COM63/66 COM64/65 COM113/16 COM114/15 COM115/14 COM116/13 COM117/12 COM118/11 COM119/10 COM120/9 Dummy23 Dummy24 Dummy25 Dummy26 Dummy27 Dummy28 Dummy29 Dummy30 Dummy31 Dummy32 Dummy33 Dummy34 Dummy35 COM121/8 COM122/7 COM123/6 COM124/5 COM125/4 COM126/3 COM127/2 COM128/1 SEG1/128 SEG2/127 SEG3/126 SEG4/125 SEG5/124 SEG6/123 SEG7/122 SEG8/121 SEG9/120 SEG10/119 SEG11/118 SEG12/117 SEG13/116 SEG14/115 SEG15/114 SEG16/113 SEG17/112 SEG18/111 SEG19/110 SEG20/109 SEG21/108 SEG22/107 SEG23/106 SEG24/105 SEG25/104 SEG26/103 SEG27/102 SEG28/101 SEG29/100 SEG30/99 SEG31/98 SEG32/97 SEG33/96 SEG34/95 SEG35/94 SEG36/93 SEG37/92 SEG38/91 SEG39/90 SEG40/89 SEG41/88 SEG42/87 X 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5089 5029 4969 4909 4848 4788 4728 4668 4608 4548 4488 4428 4352 4292 4232 4171 4111 4051 3991 3931 3835 3775 3715 3655 3595 3535 3475 3415 3354 3294 3234 3174 3114 3054 2994 2934 2873 2813 2753 2693 2633 2573 2513 2453 2392 2332 2272 2212 2152 2092 2032 1972 1912 1851 1791 1731 1671 1611 1551 1491 1431 1370 Y 571 631 691 752 812 872 932 992 1052 1112 1172 1232 1293 1353 1413 1473 1533 1593 1653 1895 1895 1895 1895 1895 1895 1895 1895 1895 1895 1895 1895 1895 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 PAD NAME SEG43/86 SEG44/85 SEG45/84 SEG46/83 SEG47/82 SEG48/81 SEG49/80 SEG50/79 SEG51/78 SEG52/77 SEG53/76 SEG54/75 SEG55/74 SEG56/73 SEG57/72 SEG58/71 SEG59/70 SEG60/69 SEG61/68 SEG62/67 SEG63/66 SEG64/65 SEG65/64 SEG66/63 SEG67/62 SEG68/61 SEG69/60 SEG70/59 SEG71/58 SEG72/57 SEG73/56 SEG74/55 SEG75/54 SEG76/53 SEG77/52 SEG78/51 SEG79/50 SEG80/49 SEG81/48 SEG82/47 SEG83/46 SEG84/45 SEG85/44 SEG86/43 SEG87/42 SEG88/41 SEG89/40 SEG90/39 SEG91/38 SEG92/37 SEG93/36 SEG94/35 SEG95/34 SEG96/33 SEG97/32 SEG98/31 SEG99/30 SEG100/29 SEG101/28 SEG102/27 SEG103/26 SEG104/25 SEG105/24 SEG106/23 SEG107/22 SEG108/21 SEG109/20 SEG110/19 SEG111/18 SEG112/17 SEG113/16 SEG114/15 SEG115/14 SEG116/13 SEG117/12 SEG118/11 SEG119/10 SEG120/9 SEG121/8 SEG122/7 SEG123/6 SEG124/5 X 1310 1250 1190 1130 1070 1010 950 889 829 769 709 649 589 529 469 409 348 288 228 168 108 48 -48 -108 -168 -228 -288 -348 -409 -469 -529 -589 -649 -709 -769 -829 -889 -950 -1010 -1070 -1130 -1190 -1250 -1310 -1370 -1431 -1491 -1551 -1611 -1671 -1731 -1791 -1851 -1912 -1972 -2032 -2092 -2152 -2212 -2272 -2332 -2392 -2453 -2513 -2573 -2633 -2693 -2753 -2813 -2873 -2934 -2994 -3054 -3114 -3174 -3234 -3294 -3354 -3415 -3475 -3535 -3595 Y 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 PAD NAME SEG125/4 SEG126/3 SEG127/2 SEG128/1 COM112/17 COM111/18 COM110/19 COM109/20 COM108/21 COM107/22 COM106/23 COM105/24 Dummy36 Dummy37 Dummy38 Dummy39 Dummy40 Dummy41 Dummy42 Dummy43 Dummy44 Dummy45 Dummy46 Dummy47 Dummy48 COM104/25 COM103/26 COM102/27 COM101/28 COM100/29 COM99/30 COM98/31 COM97/32 COM96/33 COM95/34 COM94/35 COM93/36 COM92/37 COM91/38 COM90/39 COM89/40 COM88/41 COM87/42 COM86/43 COM85/44 COM84/45 COM83/46 COM82/47 COM81/48 COM80/49 COM79/50 COM78/51 COM77/52 COM76/53 COM75/54 COM74/55 COM73/56 COM72/57 COM71/58 COM70/59 COM69/60 COM68/61 COM67/62 COM66/63 COM65/64 COM16/113 COM15/114 COM14/115 COM13/116 COM12/117 COM11/118 COM10/119 COM9/120 COM8/121 COM7/122 COM6/123 COM5/124 COM4/125 COM3/126 COM2/127 COM1/128 X -3655 -3715 -3775 -3835 -3931 -3991 -4051 -4111 -4171 -4232 -4292 -4352 -4428 -4488 -4548 -4608 -4668 -4728 -4788 -4848 -4909 -4969 -5029 -5089 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 Y 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1895 1895 1895 1895 1895 1895 1895 1895 1895 1895 1895 1895 1895 1653 1593 1533 1473 1413 1353 1293 1232 1172 1112 1052 992 932 872 812 752 691 631 571 511 451 391 331 271 210 150 90 30 -30 -90 -150 -210 -271 -331 -391 -451 -511 -571 -631 -691 -752 -812 -872 -932 -992 -1052 -1112 -1172 -1232 -1293 -1353 -1413 -1473 -1533 -1593 -1653
11
HD66750/1 HD66751 Pad Coordinate
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 PAD NAME Dummy1 Dummy2 Dummy3 Dummy4 Dummy5 Dummy6 Dummy7 Dummy8 Dummy9 Dummy10 GNDDUM1 IM1 IM1 IM0 IM0 VccDUM1 OPOFF OPOFF TEST TEST GNDDUM2 DB15 DB15 DB14 DB14 DB13 DB13 DB12 DB12 DB11 DB11 DB10 DB10 DB9 DB9 DB8 DB8 DB7 DB7 DB6 DB6 DB5 DB5 DB4 DB4 DB3 DB3 DB2 DB2 DB1 DB1 DB0 DB0 GNDDUM3 RESET* RESET* CS* CS* RS RS E/WR* E/WR* RW/RD* RW/RD* GND GND GND GND GND GND GND GND GND OSC2 OSC2 OSC1 OSC1 Vcc Vcc Vci Vci C6+ X -5269 -5089 -5029 -4969 -4909 -4848 -4788 -4728 -4668 -4608 -4454 -4394 -4334 -4210 -4150 -4086 -4026 -3966 -3842 -3782 -3722 -3658 -3598 -3474 -3414 -3290 -3230 -3106 -3046 -2922 -2862 -2738 -2678 -2554 -2494 -2370 -2310 -2186 -2126 -2002 -1942 -1818 -1758 -1634 -1574 -1450 -1390 -1266 -1206 -1083 -1022 -899 -838 -775 -715 -654 -531 -471 -347 -287 -163 -103 21 81 151 211 271 332 392 452 512 572 632 702 762 886 946 1119 1179 1342 1402 1522 Y -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1849 -1849 -1849 -1849 -1849 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 PAD NAME C6+ C6C6C5+ C5+ C5C5C4+ C4+ C4C4C3+ C3+ C3C3C2+ C2+ C2C2C1+ C1+ C1C1VLOUT VLOUT VLCD VLCD V1OUT V2OUT V3OUT V4OUT V5OUT VTEST Dummy11 Dummy12 Dummy13 Dummy14 Dummy15 Dummy16 Dummy17 Dummy18 Dummy19 Dummy20 Dummy21 Dummy22 COM1/128 COM2/127 COM3/126 COM4/125 COM5/124 COM6/123 COM7/122 COM8/121 COM9/120 COM10/119 COM11/118 COM12/117 COM13/116 COM14/115 COM15/114 COM16/113 COM17/112 COM18/111 COM19/110 COM20/109 COM21/108 COM22/107 COM23/106 COM24/105 COM25/104 COM26/103 COM27/102 COM28/101 COM29/100 COM30/99 COM31/98 COM32/97 COM33/96 COM34/95 COM35/94 COM36/93 COM37/92 X 1582 1703 1763 1883 1943 2063 2124 2244 2304 2424 2484 2605 2665 2785 2845 2965 3025 3146 3206 3326 3386 3506 3566 3687 3747 3867 3927 4047 4108 4168 4228 4288 4348 4488 4548 4608 4668 4728 4788 4848 4909 4969 5029 5089 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 Y -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1895 -1653 -1593 -1533 -1473 -1413 -1353 -1293 -1232 -1172 -1112 -1052 -992 -932 -872 -812 -752 -691 -631 -571 -511 -451 -391 -331 -271 -210 -150 -90 -30 30 90 150 210 271 331 391 451 511 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 PAD NAME COM38/91 COM39/90 COM40/89 COM41/88 COM42/87 COM43/86 COM44/85 COM45/84 COM46/83 COM47/82 COM48/81 COM49/80 COM50/79 COM51/78 COM52/77 COM53/76 COM54/75 COM55/74 COM56/73 Dummy23 Dummy24 Dummy25 Dummy26 Dummy27 Dummy28 Dummy29 Dummy30 Dummy31 Dummy32 Dummy33 Dummy34 Dummy35 COM57/72 COM58/71 COM59/70 COM60/69 COM61/68 COM62/67 COM63/66 COM64/65 COM65/64 COM66/63 COM67/62 COM68/61 COM69/60 COM70/59 COM71/58 COM72/57 COM73/56 COM74/55 COM75/54 COM76/53 COM77/52 COM78/51 COM79/50 COM80/49 COM81/48 COM82/47 COM83/46 COM84/45 COM85/44 COM86/43 COM87/42 COM88/41 COM89/40 COM90/39 COM91/38 COM92/37 COM93/36 COM94/35 COM95/34 COM96/33 COM97/32 COM98/31 COM99/30 COM100/29 COM101/28 COM102/27 COM103/26 COM104/25 COM105/24 COM106/23 X 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5269 5089 5029 4969 4909 4848 4788 4728 4668 4608 4548 4488 4428 4352 4292 4232 4171 4111 4051 3991 3931 3835 3775 3715 3655 3595 3535 3475 3415 3354 3294 3234 3174 3114 3054 2994 2934 2873 2813 2753 2693 2633 2573 2513 2453 2392 2332 2272 2212 2152 2092 2032 1972 1912 1851 1791 1731 1671 1611 1551 1491 1431 1370 Y 571 631 691 752 812 872 932 992 1052 1112 1172 1232 1293 1353 1413 1473 1533 1593 1653 1895 1895 1895 1895 1895 1895 1895 1895 1895 1895 1895 1895 1895 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 PAD NAME COM107/22 COM108/21 COM109/20 COM110/19 COM111/18 COM112/17 COM113/16 COM114/15 COM115/14 COM116/13 COM117/12 COM118/11 COM119/10 COM120/9 COM121/8 COM122/7 COM123/6 COM124/5 COM125/4 COM126/3 COM127/2 COM128/1 SEG1/128 SEG2/127 SEG3/126 SEG4/125 SEG5/124 SEG6/123 SEG7/122 SEG8/121 SEG9/120 SEG10/119 SEG11/118 SEG12/117 SEG13/116 SEG14/115 SEG15/114 SEG16/113 SEG17/112 SEG18/111 SEG19/110 SEG20/109 SEG21/108 SEG22/107 SEG23/106 SEG24/105 SEG25/104 SEG26/103 SEG27/102 SEG28/101 SEG29/100 SEG30/99 SEG31/98 SEG32/97 SEG33/96 SEG34/95 SEG35/94 SEG36/93 SEG37/92 SEG38/91 SEG39/90 SEG40/89 SEG41/88 SEG42/87 SEG43/86 SEG44/85 SEG45/84 SEG46/83 SEG47/82 SEG48/81 SEG49/80 SEG50/79 SEG51/78 SEG52/77 SEG53/76 SEG54/75 SEG55/74 SEG56/73 SEG57/72 SEG58/71 SEG59/70 SEG60/69 X 1310 1250 1190 1130 1070 1010 950 889 829 769 709 649 589 529 469 409 348 288 228 168 108 48 -48 -108 -168 -228 -288 -348 -409 -469 -529 -589 -649 -709 -769 -829 -889 -950 -1010 -1070 -1130 -1190 -1250 -1310 -1370 -1431 -1491 -1551 -1611 -1671 -1731 -1791 -1851 -1912 -1972 -2032 -2092 -2152 -2212 -2272 -2332 -2392 -2453 -2513 -2573 -2633 -2693 -2753 -2813 -2873 -2934 -2994 -3054 -3114 -3174 -3234 -3294 -3354 -3415 -3475 -3535 -3595 Y 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 PAD NAME SEG61/68 SEG62/67 SEG63/66 SEG64/65 SEG65/64 SEG66/63 SEG67/62 SEG68/61 SEG69/60 SEG70/59 SEG71/58 SEG72/57 Dummy36 Dummy37 Dummy38 Dummy39 Dummy40 Dummy41 Dummy42 Dummy43 Dummy44 Dummy45 Dummy46 Dummy47 Dummy48 SEG73/56 SEG74/55 SEG75/54 SEG76/53 SEG77/52 SEG78/51 SEG79/50 SEG80/49 SEG81/48 SEG82/47 SEG83/46 SEG84/45 SEG85/44 SEG86/43 SEG87/42 SEG88/41 SEG89/40 SEG90/39 SEG91/38 SEG92/37 SEG93/36 SEG94/35 SEG95/34 SEG96/33 SEG97/32 SEG98/31 SEG99/30 SEG100/29 SEG101/28 SEG102/27 SEG103/26 SEG104/25 SEG105/24 SEG106/23 SEG107/22 SEG108/21 SEG109/20 SEG110/19 SEG111/18 SEG112/17 SEG113/16 SEG114/15 SEG115/14 SEG116/13 SEG117/12 SEG118/11 SEG119/10 SEG120/9 SEG121/8 SEG122/7 SEG123/6 SEG124/5 SEG125/4 SEG126/3 SEG127/2 SEG128/1 X -3655 -3715 -3775 -3835 -3931 -3991 -4051 -4111 -4171 -4232 -4292 -4352 -4428 -4488 -4548 -4608 -4668 -4728 -4788 -4848 -4909 -4969 -5029 -5089 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 -5269 Y 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1895 1895 1895 1895 1895 1895 1895 1895 1895 1895 1895 1895 1895 1653 1593 1533 1473 1413 1353 1293 1232 1172 1112 1052 992 932 872 812 752 691 631 571 511 451 391 331 271 210 150 90 30 -30 -90 -150 -210 -271 -331 -391 -451 -511 -571 -631 -691 -752 -812 -872 -932 -992 -1052 -1112 -1172 -1232 -1293 -1353 -1413 -1473 -1533 -1593 -1653
12
HD66750/1
TCP Dimensions (HD66750TB0)
Bending slit 4.0 mm HD66750
IM1 IM0 OPOFF TEST DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RESET* CS* RS E/WR* RW/RD* GND OSC2 OSC1 Vcc Vci C6+ C6C5+ C5C4+ C4C3+ C3C2+ C2C1+ C1VLOUT VLCD V1OUT V2OUT V3OUT V4OUT V5OUT VTEST Dummy COM1/128 COM16/113 COM65/64
(HD66751)
(Dummy) (SEG128/1) (SEG127/2 (SEG126/3) (SEG125/4)
0.65-mm pitch
HD66750 HD66750
COM104/25 SEG128/1 SEG127/2 SEG126/3 SEG125/4
I/O, Power supply 0.65P x (50 - 1) = 31.85 mm
0.14-mm pitch (SEG4/125) LCD drive (SEG3/126)
(SEG2/127) (SEG1/128) (COM128/1) (COM127/2) (COM126/3)
SEG4/125 SEG3/126 SEG2/127 SEG1/128 COM128/1 COM113/16 COM64/65
0.12P x (258 - 1) = 30.784 mm
HITACHI HITACHI
COM17/112 Dummy
(COM3/126) (COM2/127) (COM1/128) (Dummy)
13
HD66750/1
Pin Functions
Table 2
Signals IM1, IM0
Pin Functional Description
Number of Pins I/O 2 I Connected to GND or VCC Functions Selects the MPU interface mode:
IM1 GND GND Vcc Vcc IM0 GND Vcc GND Vcc MPU interface mode 68-system 16-bit bus interface 68-system 8-bit bus interface 80-system 16-bit bus interface 80-system 8-bit bus interface
CS*
1
I
MPU
Selects the HD66750/1: Low: HD66750/1 is selected and can be accessed High: HD66750/1 is not selected and cannot be accessed Must be fixed at GND level when not in use. Selects the register. Low: Index/status High: Control
RS E/WR*
1 1
I I
MPU MPU
For a 68-system bus interface, serves as an enable signal to activate data read/write operation. For an 80-system bus interface, serves as a write strobe signal and writes data at the low level. For a 68-system bus interface, serves as a signal to select data read/write operation. Low: Write High: Read For an 80-system bus interface, serves as a read strobe signal and reads data at the low level. Serves as a 16-bit bidirectional data bus. For an 8-bit bus interface, data transfer uses DB15DB8; fix unused DB7-DB0 to the Vcc or GND level. Output signals for common drive: All the unused pins output unselected waveforms. In the display-off period (D = 0), sleep mode (SLP = 1), or standby mode (STB = 1), all pins output GND level. The CMS bit can change the shift direction of the common signal. For example, if CMS = 0, COM1/128 is COM1, and COM128/1 is COM128. If CMS = 1, COM1/128 is COM128, and COM128/1 is COM1. Note that the start position of the common output is shifted by CN1CN0 bits. Output signals for segment drive. In the display-off period (D = 0), sleep mode (SLP = 1), or standby mode (STB = 1), all pins output GND level. The SGS bit can change the shift direction of the segment signal. For example, if SGS = 0, SEG1/128 is SEG1. If SGS = 1, SEG1/128 is SEG128.
RW/RD*
1
I
MPU
DB0DB15
16
I/O
MPU
COM1/128 128 COM128/1
O
LCD
SEG1/128 SEG128/1
128
O
LCD
14
HD66750/1
Table 2
Signals V1OUT- V5OUT
Pin Functional
Number of Pins 5 I/O
Description
(cont)
Functions Used for output from the internal operational amplifiers when they are used (OPOFF = GND); attach a capacitor to stabilize the output. When the amplifiers are not used (OPOFF = VCC), V1 to V5 voltages can be supplied to these pins externally. Power supply for LCD drive. VLCD - GND = 17 V max. VCC: +1.8 V to +5.5 V; GND (logic): 0 V
Connected to I or O Open or external bleeder-resistor
VLCD VCC, GND OSC1, OSC2 Vci
1 2 2
-- --
Power supply Power supply
I or O OscillationFor R-C oscillation using an external resistor, connect resistor or clock an external resistor. For external clock supply, input clock pulses to OSC1. I Power supply Inputs a reference voltage and supplies power to the booster; generates the liquid crystal display drive voltage from the operating voltage. The boosting output voltage must not be larger than the absolute maximum ratings. Must be left disconnected when the booster is not used.
1
VLOUT
1
O
VLCD pin/booster Potential difference between Vci and GND is two- to capacitance seven-times-boosted and then output. Magnitude of boost is selected by instruction. Booster capacitance Booster capacitance Booster capacitance Booster capacitance Booster capacitance Booster capacitance External capacitance should be connected here for boosting. External capacitance should be connected here for boosting. External capacitance should be connected here for boosting. External capacitance should be connected here for boosting. External capacitance should be connected here for boosting. External capacitance should be connected here for boosting.
C1+, C1- C2+, C2- C3+, C3- C4+, C4- C5+, C5- C6+, C6- RESET* OPOFF
2 2 2 2 2 2 1 1
-- -- -- -- -- -- I I
MPU or external Reset pin. Initializes the LSI when low. Must be reset R-C circuit after power-on. VCC or GND Turns the internal operational amplifier off when OPOFF = VCC, and turns it on when OPOFF = GND. If the amplifier is turned off (OPOFF = VCC), V1 to V5 must be supplied to the V1OUT to V5OUT pins. Outputs the internal VCC level; shorting this pin sets the adjacent input pin to the VCC level. Outputs the internal GND level; shorting this pin sets the adjacent input pin to the GND level. Dummy pad. Must be left disconnected. Test pin. Must be fixed at GND level. Test pin. Must be left disconnected.
VccDUM GNDDUM Dummy TEST VTEST
2 4 4 1 1
O O -- I --
Input pins Input pins -- GND --
15
HD66750/1
Block Function Description
System Interface The HD66750/1 has four high-speed system interfaces: an 80-system 16-bit/8-bit bus and a 68-system 16bit/8-bit bus. The interface mode is selected by the IM1-0 pins. The HD66750/1 has three 16-bit registers: an index register (IR), a write data register (WDR), and a read data register (RDR). The IR stores index information from the control registers and the CGRAM. The WDR temporarily stores data to be written into control registers and the CGRAM, and the RDR temporarily stores data read from the CGRAM. Data written into the CGRAM from the MPU is first written into the WDR and then is automatically written into the CGRAM by internal operation. Data is read through the RDR when reading from the CGRAM, and the first read data is invalid and the second and the following data are normal. When a logic operation is performed inside of the HD66750/1 by using the display data set in the CGRAM and the data written from the MPU, the data read through the RDR is used. Accordingly, the MPU does not need to read data twice nor to fetch the read data into the MPU. This enables high-speed processing. Execution time for instruction excluding oscillation start is 0 clock cycle and instructions can be written in succession. Table 3
R/W Bits 0 1 0 1
Register Selection by RS and R/W Bits
RS Bits 0 0 1 1 Operations Writes indexes into IR Disabled Writes into control registers and CGRAM through WDR Reads from CGRAM through RDR
Bit Operation The HD66750/1 supports the following functions: a bit rotation function that writes the data written from the MPU into the CGRAM by moving the display position in bit units, a write data mask function that selects and writes data into the CGRAM in bit units, and a logic operation function that performs logic operations on the display data set in the CGRAM and writes into the CGRAM. With the 16-bit bus interface, these functions can greatly reduce the processing loads of the MPU graphics software and can rewrite the display data in the CGRAM at high speed. For details, see the Graphics Operation Function section. Address Counter (AC) The address counter (AC) assigns addresses to the CGRAM. When an address set instruction is written into the IR, the address information is sent from the IR to the AC. After writing into the CGRAM, the AC is automatically incremented by 1 (or decremented by 1). After reading from the data, the RDM bit automatically updates or does not update the AC.
16
HD66750/1
Graphic RAM (CGRAM) The graphic RAM (CGRAM) stores bit-pattern data of 128 x 120 dots. It has two bits/pixel and 4096-byte capacity. Grayscale Control Circuit The grayscale control circuit performs four-grayscale control with the frame rate control (FRC) method for four-monochrome grayscale display. For details, see the Four Grayscale Display Function section. Timing Generator The timing generator generates timing signals for the operation of internal circuits such as the CGRAM. The RAM read timing for display and internal operation timing by MPU access are generated separately to avoid interference with one another. Oscillation Circuit (OSC) The HD66750/1 can provide R-C oscillation simply through the addition of an external oscillation-resistor between the OSC1 and OSC2 pins. The appropriate oscillation frequency for operating voltage, display size, and frame frequency can be obtained by adjusting the external-resistor value. Clock pulses can also be supplied externally. Since R-C oscillation stops during the standby mode, current consumption can be reduced. For details, see the Oscillation Circuit section. Liquid Crystal Display Driver Circuit The liquid crystal display driver circuit consists of 128 common signal drivers (COM1 to COM128) and 128 segment signal drivers (SEG1 to SEG128). When the number of lines are selected by a program, the required common signal drivers automatically output drive waveforms, while the other common signal drivers continue to output unselected waveforms. Display pattern data is latched when 128-bit data has arrived. The latched data then enables the segment signal drivers to generate drive waveform outputs. The shift direction of 128-bit data can be changed by the SGS bit. The shift direction for the common driver can also be changed by the CMS bit by selecting an appropriate direction for the device mounting configuration. When multiplexing drive is not used, or during the standby or sleep mode, all the above common and segment signal drivers output the GND level, halting the display. Booster (DC-DC Converter) The booster generates two-, five-, six-, or seven-times voltage input to the Vci pin. With this, both the internal logic units and LCD drivers can be controlled with a single power supply. Boost output level from twice to seven-times boost can be selected by software. For details, see the Power Supply for Liquid Crystal Display Drive section.
17
HD66750/1
V-Pin Voltage Follower A voltage follower for each voltage level (V1 to V5) reduces current consumption by the LCD drive power supply circuit. No external resistors are required because of the internal bleeder-resistor, which generates different levels of LCD drive voltage. This internal bleeder-resistor can be software-specified from 1/4 bias to 1/11 bias, according to the liquid crystal display drive duty value. The voltage followers can be turned off while multiplexing drive is not being used. For details, see the Power Supply for Liquid Crystal Display Drive section. Contrast Adjuster The contrast adjuster can be used to adjust LCD contrast in 64 steps by varying the LCD drive voltage by software. This can be used to select an appropriate LCD brightness or to compensate for temperature.
18
HD66750/1
CGRAM Address Map
Table 4 Relationship between Display Position and CGRAM Address
SEG16/113 SEG17/112 SEG24/105 SEG4/125 SEG3/126 SEG7/122 SEG1/128 SEG2/127 SEG6/123 SEG9/120 SEG5/124 SEG8/121 SEG121/8 SEG128/1
D15 D0
Segment Driver SGS="0" SGS="1" COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM125 COM126 COM127 COM128

D0
D1
D2
D3
D4
D5
D6
D7 D8
D8 D7
D9 D10 D11 D12 D13 D14 D15 D0 D6 D5 D4 D3 D2 D1
D1
Bit

D15 D0 D0
D1

D15 D0

D0
D1

D15 D14 D13 D12 D11 D10 D9
D0 D15 D14
D15 D14
D15 D14
Address: "000"H Address: "010"H Address: "020"H Address: "030"H Address: "040"H Address: "050"H Address: "060"H Address: "070"H Address: "080"H Address: "090"H Address: "0A0"H Address: "0B0"H Address: "0C0"H Address: "0D0"H Address: "0E0"H Address: "0F0"H Address: "100"H Address: "110"H Address: "120"H Address: "130"H Address: "7C0"H Address: "7D0"H Address: "7E0"H Address: "7F0"H
"001"H "011"H "021"H "031"H "041"H "051"H "061"H "071"H "081"H "091"H "0A1"H "0B1"H "0C1"H "0D1"H "0E1"H "0F1"H "101"H "111"H "121"H "131"H "7C1"H "7D1"H "7E1"H "7F1"H
"002"H "012"H "022"H "032"H "042"H "052"H "062"H "072"H "082"H "092"H "0A2"H "0B2"H "0C2"H "0D2"H "0E2"H "0F2"H "102"H "112"H "122"H "132"H "7C2"H "7D2"H "7E2"H "7F2"H
"00F"H "01F"H "02F"H "03F"H "04F"H "05F"H "06F"H "07F"H "08F"H "09F"H "0AF"H "0BF"H "0CF"H "0DF"H "0EF"H "0FF"H "10F"H "11F"H "12F"H "13F"H "7CF"H "7DF"H "7EF"H "7FF"H
Table 5 Relationship between CGRAM Data and Display Contents
Upper Bit 0 0 1 1 Note: Lower Bit 0 1 0 1 LCD Non-selection display (unlit) 1/3- or 1/2-level grayscale display (selected by the GS bit) 2/3-level grayscale display Selection display (lit)
Upper bits: DB15, DB13, DB11, DB9, DB7, DB5, DB3, DB1 Lower bits: DB14, DB12, DB10, DB8, DB6, DB4, DB2, DB0
HITACHI
19
HD66750/1
Instructions
Outline The HD66750/1 uses the 16-bit bus architecture. Before the internal operation of the HD66750/1 starts, control information is temporarily stored in the registers described below to allow high-speed interfacing with a high-performance microcomputer. The internal operation of the HD66750/1 is determined by signals sent from the microcomputer. These signals, which include the register selection signal (RS), the read/write signal (R/W), and the data bus signals (DB15 to DB7), make up the HD66750/1 instructions. There are seven categories of instructions that: Specify the index Read the status Control the display Control power management Process the graphics data Set internal CGRAM addresses Transfer data to and from the internal CGRAM
Normally, instructions that write data are used the most. However, an auto-update of internal CGRAM addresses after each data write can lighten the microcomputer program load. Because instructions are executed in 0 cycles, they can be written in succession.
20
HD66750/1
Instruction Descriptions
Index The index instruction specifies the RAM control indexes (R00 to R12). It sets the register number in the range of 00000 to 10010 in biniary form.
R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
*
*
*
*
*
*
*
*
*
*
*
ID4 ID3 ID2 ID1 ID0
Figure 1 Index Instruction Status Read The status read instruction reads the internal status of the HD66750/1. L60: Indicate the driving raster-row position where the liquid crystal display is being driven. C50: Read the contrast setting values (CT50).
R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
0
L6
L5
L4
L3
L2
L1
L0
0
0
C5
C4
C3
C2
C1
C0
Figure 2 Status Read Instruction Start Oscillation The start oscillation instruction restarts the oscillator from the halt state in the standby mode. After issuing this instruction, wait at least 10 ms for oscillation to stabilize before issuing the next instruction. (See the Standby Mode section.) If this register is read forcibly when R/W = 1, 0750H is read.
R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 1
1 1
* 0
* 0
* 0
* 0
* 0
* 1
* 1
* 1
* 0
* 1
* 0
* 1
* 0
* 0
* 0
1 0
Figure 3 Start Oscillation Instruction
21
HD66750/1
Driver Output Control CMS: Selects the output shift direction of a common driver. When CMS = 0, COM1/128 shifts to COM1, and COM128/1 to COM128. When CMS = 1, COM1/128 shifts to COM128, and COM128/1 to COM1. Output position of a common driver shifts depending on the CN bit setting. SGS: Selects the output shift direction of a segment driver. When SGS = 0, SEG1/128 shifts to SEG1, and SEG128/1 to SEG128. When SGS = 1, SEG1/128 shifts to SEG128, and SEG128/1 to SEG1. CN: When CN = 1, the display position is shifted down by 32 raster-rows and display starts from COM33. When the liquid crystal is driven at a low duty ratio in the system wait state, it can be partially displayed at the center of the screen. For details, see the Partial-display-on Function section. NL3-0: Specify the LCD drive duty ratio. The duty ratio can be adjusted for every eight raster-rows. CGRAM address mapping does not depend on the setting value of the drive duty ratio.
R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
*
*
*
*
*
*
CMS SGS
*
CN
*
*
NL3 NL2 NL1 NL0
Figure 4 Driver Output Control Instruction Table 6
NL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 NL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
NL Bits and Drive Duty
NL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 NL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Display Size 128 x 8 dots 128 x 16 dots 128 x 24 dots 128 x 32 dots 128 x 40 dots 128 x 48 dots 128 x 56 dots 128 x 64 dots 128 x 72 dots 128 x 80 dots 128 x 88 dots 128 x 96 dots 128 x 104 dots 128 x 112 dots 128 x 120 dots 128 x 128 dots LCD Drive Duty 1/8 Duty 1/16 Duty 1/24 Duty 1/32 Duty 1/40 Duty 1/48 Duty 1/56 Duty 1/64 Duty 1/72 Duty 1/80 Duty 1/88 Duty 1/96 Duty 1/104 Duty 1/112 Duty 1/120 Duty 1/128 Duty Common Driver Used COM1COM8 COM1COM16 COM1COM24 COM1COM32 COM1COM40 COM1COM48 COM1COM56 COM1COM64 COM1COM72 COM1COM80 COM1COM88 COM1COM96 COM1COM104 COM1COM112 COM1COM120 COM1COM128
22
HD66750/1
LCD-Driving-Waveform Control B/C: When B/C = 0, a B-pattern waveform is generated and alternates in every frame for LCD drive. When B/C = 1, a C-pattern waveform is generated and alternates in each raster-row specified by bits EOR and NW4NW0 in the LCD-driving-waveform control register. For details, see the n-raster-row Reversed AC Drive section. EOR: When the C-pattern waveform is set (B/C = 1) and EOR = 1, the odd/even frame-select signals and the n-raster-row reversed signals are EORed for alternating drive. EOR is used when the LCD is not alternated by combining the set values of the LCD drive duty ratio and the n raster-row. For details, see the n-raster-row Reversed AC Drive section. NW40: Specify the number of raster-rows n that will alternate at the C-pattern waveform setting (B/C = 1). NW4NW0 alternate for every set value + 1 raster-row, and the first to the 32nd raster-rows can be selected.
R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
*
*
*
*
*
*
*
*
*
B/C EOR NW4 NW3 NW2 NW1 NW0
Figure 5 LCD-Driving-Waveform Control Instruction
23
HD66750/1
Table 7 Common Driver Pin Function
Common Driver Pin Function CN = 0 (Normal Output) Common Driver Pin COM1/128 COM8/121 COM9/120 COM16/113 COM17/112 COM24/105 COM25/104 COM32/97 COM33/96 COM40/89 COM41/88 COM48/81 COM49/80 COM56/73 COM57/72 COM64/65 COM65/64 COM72/57 COM73/56 COM80/49 COM81/48 COM88/41 COM89/40 COM96/33 CMS = 0 COM1 COM8 COM9 COM16 COM17 COM24 COM25 COM32 COM33 COM40 COM41 COM48 COM49 COM56 COM57 COM64 COM65 COM72 COM73 COM80 COM81 COM88 COM89 COM96 COM33 COM41 COM40 COM64 COM49 COM48 COM56 COM57 COM1 COM57 COM56 COM48 COM49 COM9 COM8 COM65 COM64 COM40 COM41 COM17 COM16 COM73 COM72 COM32 COM33 COM25 COM24 COM81 COM80 COM24 COM25 COM33 COM32 COM89 COM88 COM16 COM17 COM41 COM40 COM97 COM96 COM8 COM9 COM49 COM48 COM105 COM104 COM113 COM112 COM120 (COM121) (COM128) COM1 COM57 COM56 COM121 COM120 COM112 COM113 COM73 COM72 COM65 COM64 CMS = 1 COM128 COM104 COM105 COM81 COM80 CN = 1 (Center Output) CMS = 0 COM97 COM89 COM88 CMS = 1 COM96
24
HD66750/1
Table 7 Common Driver Pin Function (cont)
Common Driver Pin Function CN = 0 (Normal Output) Common Driver Pin COM97/32 COM104/25 COM105/24 COM112/17 COM113/16 COM120/9 COM121/8 COM128/1 CMS = 0 COM97 COM104 COM105 COM112 COM113 COM120 COM121 COM128 COM1 COM9 COM8 COM96 COM17 COM16 COM88 COM89 COM97 COM25 COM24 COM80 COM81 COM105 COM104 CMS = 1 COM32 COM72 COM73 COM113 COM112 CN = 1 (Center Output) CMS = 0 COM65 CMS = 1 (COM128) (COM121) COM120
Power Control BS20: The LCD drive bias value is set within the range of a 1/4 to 1/11 bias. The LCD drive bias value can be selected according to its drive duty ratio and voltage. For details, see the Liquid Crystal Display Drive Bias Selector section. BT1-0: The output factor of V5OUT between two-times, three-times, four-times, five-times, six-times, and seven-times boost is switched. The LCD drive voltage level can be selected according to its drive duty ratio and bias. Lower amplification of the booster consumes less current. DC1-0: The operating frequency in the booster is selected. When the boosting operating frequency is high, the driving ability of the booster and the display quality become high, but the current consumption is increased. Adjust the frequency considering the display quality and the current consumption. AP1-0: The amount of fixed current from the fixed current source in the operational amplifier for V pins (V1 to V5) is adjusted. When the amount of fixed current is large, the driving ability of the booster and the display quality become high, but the current consumption is increased. Adjust the fixed current considering the display quality and the current consumption. During no display, when AP10 = 00, the current consumption can be reduced by ending the operational amplifier and booster operation.
25
HD66750/1
Table 8
BS2 0 0 0 0 1 1 1 1
BS Bits and LCD Drive Bias Value
BS1 0 0 1 1 0 0 1 1 BS0 0 1 0 1 0 1 0 1 LCD Drive Bias Value 1/11 bias drive 1/10 bias drive 1/9 bias drive 1/8 bias drive 1/7 bias drive 1/6 bias drive 1/5 bias drive 1/4 bias drive
Table 9
BT1 0 0 1 1
BT Bits and Output Level
BT0 0 1 0 1 V5OUT Output Level Two-times boost Five-times boost Six-times boost Seven-times boost
Table 10
DC1 0 0 1 1
DC Bits and Operating Clock Frequency
DC0 0 1 0 1 Operating Clock Frequency in the Booster 32-divided clock 16-divided clock 8-divided clock 4-divided clock
Table 11
AP1 0 0 1 1
AP Bits and Amount of Fixed Current
AP0 0 1 0 1 Amount of Fixed Current in the Operational Amplifier Operational amplifier and booster do not operate. Small Middle Large
SLP: When SLP = 1, the HD66750/1 enters the sleep mode, where the internal display operations are halted except for the R-C oscillator, thus reducing current consumption. For details, see the Sleep Mode section. Only the following instructions can be executed during the sleep mode. Power control (BS20, BT10, DC10, AP10, SLP, and STB bits) During the sleep mode, the other CGRAM data and instructions cannot be updated although they are
26
HD66750/1
retained. STB: When STB = 1, the HD66750/1 enters the standby mode, where display operation completely stops, halting all the internal operations including the internal R-C oscillator. Further, no external clock pulses are supplied. For details, see the Standby Mode section. Only the following instructions can be executed during the standby mode. a. Standby mode cancel (STB = 0) b. Start oscillation c. Power control (BS20, BT10, DC10, AP10, SLP, and STB bits) During the standby mode, the CGRAM data and instructions may be lost. To prevent this, they must be set again after the standby mode is canceled.
R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
*
*
*
BS2 BS1 BS0 BT1 BT0
*
*
DC1 DC0 AP1 AP0 SLP STB
Figure 6 Power Control Instruction
27
HD66750/1
Contrast Control CT50: These bits control the LCD drive voltage (potential difference between V1 and GND) to adjust 64-step contrast. For details, see the Contrast Adjuster section.
R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
*
*
*
*
*
*
*
*
*
*
CT5 CT4 CT3 CT2 CT1 CT0
Figure 7 Contrast Control Instruction
HD66750/1
VLCD VR R R R0 R R GND
+ + + + + -
V1 V2 V3
V4 V5 GND
Figure 8 Contrast Adjuster
28
HD66750/1
Table 12 CT Bits and Variable Resistor Value of Contrast Adjuster
CT Set Value CT5 0 0 0 0 0 CT4 0 0 0 0 0 CT3 0 0 0 0 0 CT2 0 0 0 0 1 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1 0 0 1 1 0 1 0 CT1 0 0 1 1 0 CT0 0 1 0 1 0 Variable Resistor (VR) 3.20 x R 3.15 x R 3.10 x R 3.05 x R 3.00 x R 1.65 x R 1.60 x R 1.55 x R 1.50 x R 0.15 x R 0.10 x R 0.05 x R
Entry Mode Rotation The write data sent from the microcomputer is modified in the HD66750/1 and written to the CGRAM. The display data in the CGRAM can be quickly rewritten to reduce the load of the microcomputer software processing. For details, see the Graphics Operation Function section. I/D: When I/D = 1, the address counter (AC) is automatically incremented by 1 after the data is written to the CGRAM. When I/D = 0, the AC is automatically decremented by 1 after the data is written to the CGRAM. AM10: Set the automatic update method of the AC after the data is written to the CGRAM. When AM10 = 00, the data is continuously written in parallel. When AM10 = 01, the data is continuously written vertically. When AM10 = 10, the data is continuously written vertically with two-word width (32-bit length). LG10: Write again the data read from the CGRAM and the data written from the microcomputer to the CGRAM by a logical operation. When LG10 = 00, replace (no logical operation) is done. ORed when LG10 = 01, ANDed when LG10 = 10, and EORed when LG10 = 11. RT20: Write the data sent from the microcomputer to the CGRAM by rotating in a bit unit. RT30 specify rotation. For example, when RT20 = 001, the data is rotated in the upper side by two bits. When RT20 = 111, the data is rotated in the upper side by 14 bits. The upper bit overflown in the most significant bit (MSB) side is rotated in the least significant bit (LSB) side.
29
HD66750/1
R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0
1 1
* *
* *
* *
* *
* *
* *
* *
* *
* *
* *
* *
I/D AM1 AM0 LG1 LG0 * * RT2 RT1 RT0
Figure 9 Entry Mode and Rotation Instructions
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Write data sent from the microcomputer (DB150) Rotation (RT20 = 001)
0
0
0
1
1
1
0
0
1
1
1
0
0
0
1
1
0
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
Logical operation (LG10)
Logical operation
LG10 = 00: Replace LG10 = 01: ORed LG10 = 10: ANDed LG10 = 11: EORed
Write data mask* (WM150)
Write data mask (WM150)
CGRAM
Note: The write data mask (WM150) is set by the register in the RAM Write Data Mask section.
Figure 10 Logical Operation and Rotation for the CGRAM
30
HD66750/1
Display Control PS10: When PS10 = 01, only the upper eight raster-rows (COM1COM8) are fixed-displayed in vertical smooth scrolling, and the other display raster-rows are smooth-scrolled. When PS10 = 10, the upper 16 raster-rows (COM1COM16) are fixed-displayed. When PS10 = 11, the upper 24 raster-rows (COM1 COM24) are fixed-displayed. For details, see the Partial Smooth Scroll Display Function section. DHE: When DHE = 1, the double height between raster-rows specified in the Double-height Display Position section is displayed. For details, see the Double-height Display section. GS: When GS = 0, the grayscale level at a weak-colored display (DB = 01) is 1/3. When GS = 1, the grayscale level at weak-colored display is 1/2, and at strong-colored display (when DB = 10) it is 2/3. REV: Displays all character and graphics display sections with black-and-white reversal when REV = 1. For details, see the Reversed Display Function section. D: Display is on when D = 1 and off when D = 0. When off, the display data remains in the CGRAM, and can be displayed instantly by setting D = 1. When D is 0, the display is off with the SEG1 to SEG128 outputs and COM1 to COM128 outputs set to the GND level. Because of this, the HD66750/1 can control the charging current for the LCD with AC driving.
R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
*
*
*
*
*
*
*
*
*
*
PS1 PS0 DHE GS REV
D
Figure 11 Display Control Instruction
31
HD66750/1
Cursor Control C: When C = 1, the window cursor display is started. The display mode is selected by the CM10 bits, and the display area is specified in a dot unit by the horizontal cursor position register (HS60 and HE60 bits) and vertical cursor position register (VS60 and VE60 bits). For details, see the Window Cursor Display section. CM10: The display mode of the window cursor is selected. These bits can display a white-blink cursor, black-blink cursor, black-and-white reversed cursor, and black-and-white-reversed blink cursor.
R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
*
*
*
*
*
*
*
*
*
*
*
*
*
C
CM1 CM0
Figure 12 Cursor Control Instruction Table 13
CM1 0 0 1 1 CM0 0 1 0 1
CM Bits and Window Cursor Display Mode
Window Cursor Display Mode White-blink cursor (alternately blinking between the normal display and an all-white display (all unlit)) Black-blink cursor (alternately blinking between the normal display and an all-black display (all lit)) Black-and-white reversed cursor (black-and-white-reversed normal display (no blinking)) Black-and-white-reversed blink cursor (alternately blinking the black-and-whitereversed normal display)
Double-height Display Position DS60: Specify any common raster-row position where the double-height display starts. Note that no scrolling is done by vertical scrolling. For details, see the Double-height Display section. DE6-0: Specify any common raster-row position where the double-height display ends. Set the end position of the double-height display after the start position of the double-height display, satisfying the relationship DS60 DE60. When the area specifying the double height has an odd number of rasterrows, the double-height display is done for the DE60 + 1 raster-rows. When the double-height display is not used, set the DHE bit in the display-control instruction register to 0.
R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
*
DE6 DE5 DE4 DE3 DE2 DE1 DE0
*
DS6 DS5 DS4 DS3 DS2 DS1 DS0
Figure 13 Double-height Display Position Instruction
32
HD66750/1
Vertical Scroll Control SL60: Specify the display start raster-row for vertical smooth scrolling. Any raster-row from the first to 128th can be selected (table 14). After the 128th raster-row is displayed, the display restarts from the first raster-row. For details, see the Vertical Smooth Scroll section. In partial smooth scrolling, these bits specify the display start raster-row of the next fixed-display rasterrow. For details, see the Partial Smooth Scroll Display Function section.
R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
*
*
*
*
*
*
*
*
*
SL6 SL5 SL4 SL3 SL2 SL1 SL0
Figure 14 Vertical Scroll Control Instruction Table 14
SL6 0 0 0 0 0 : 1 1
SL Bits and Display-start Raster-row
SL5 0 0 0 0 0 : 1 1 SL4 0 0 0 0 0 : 1 1 SL3 0 0 0 0 0 : 1 1 SL2 0 0 0 0 1 : 1 1 SL1 0 0 1 1 0 : 1 1 SL0 0 1 0 1 0 : 0 1 Display-start Raster-row 1st raster-row 2nd raster-row 3rd raster-row 4th raster-row 5th raster-row : 127th raster-row 128th raster-row
33
HD66750/1
Horizontal Cursor Position Vertical Cursor Position HS6-0: Specify the start position for horizontally displaying the window cursor in a dot unit. The cursor is displayed from the 'set value + 1' dot. Ensure that HS60 HE60. HE6-0: Specify the end position for horizontally displaying the window cursor in a dot unit. The cursor is displayed to the 'set value + 1' dot. Ensure that HS60 HE60. VS6-0: Specify the start position for vertically displaying the window cursor in a dot unit. The cursor is displayed from the 'set value + 1' dot. Ensure that VS60 VE60. VE6-0: Specify the end position for vertically displaying the window cursor in a dot unit. The cursor is displayed to the 'set value + 1' dot. Ensure that VS60 VE60. In vertical scrolling, rewrite VS60 and VE60 since this window cursor does not move vertically.
R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0
1 1
* *
HE6 HE5 HE4 HE3 HE2 HE1 HE0 VE6 VE5 VE4 VE3 VE2 VE1 VE0
* *
HS6 HS5 HS4 HS3 HS2 HS1 HS0 VS6 VS5 VS4 VS3 VS2 VS1 VS0
Figure 15 Horizontal Cursor Position and Vertical Cursor Position Instructions
HS1+1 HE1+1
VS1+1
Window cursor
VE1+1
Figure 16 Window Cursor Position
34
HD66750/1
RAM Write Data Mask WM15-0: In writing to the CGRAM, these bits mask writing in a bit unit. When WM15 = 1, this bit masks the write data of DB15 and does not write to the CGRAM. Similarly, the WM140 bits mask the write data of DB140 in a bit unit. However, when AM = 10, the write data is masked with the set values of VM150 for the odd-times CGRAM write. It is also masked automatically with the reversed set values of VM150 for the even-times CGRAM write. For details, see the Graphics Operation Function section.
R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
VM VM 15 14
VM 13
VM 12
VM VM 11 10
VM 9
VM VM 8 7
VM 6
VM VM 5 4
VM 3
VM VM 2 1
VM 0
Figure 17 RAM Write Data Mask Instruction RAM Address Set AD10-0: Initially set CGRAM addresses to the address counter (AC). Once the CGRAM data is written, the AC is automatically updated according to the AM10 and I/D bit settings. This allows consecutive accesses without resetting addresses. Once the CGRAM data is read, the AC is not automatically updated. CGRAM address setting is not allowed in the sleep mode or standby mode.
R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
*
*
*
*
*
AD AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 10
Figure 18 RAM Address Set Instruction Table 15
AD10AD0 "000"H"00F"H "010"H"01F"H "020"H"02F"H "030"H"03F"H : "760"H"76F"H "770"H"77F"H "780"H"78F"H "790"H"79F"H "7A0"H"7AF"H "7B0"H"7BF"H "7C0"H"7CF"H "7D0"H"7DF"H "7E0"H"7EF"H "7F0"H"7FF"H
AD Bits and CGRAM Settings
CGRAM Setting Bitmap data for COM1 Bitmap data for COM2 Bitmap data for COM3 Bitmap data for COM4 : Bitmap data for COM119 Bitmap data for COM120 121st raster-row data (appeared at vertical scrolling) 122nd raster-row data (appeared at vertical scrolling) 123rd raster-row data (appeared at vertical scrolling) 124th raster-row data (appeared at vertical scrolling) 125th raster-row data (appeared at vertical scrolling) 126th raster-row data (appeared at vertical scrolling) 127th raster-row data (appeared at vertical scrolling) 128th raster-row data (appeared at vertical scrolling)
35
HD66750/1
Write Data to CGRAM WD15-0 : Write 16-bit data to the CGRAM. After a write, the address is automatically updated according to the AM10 and I/D bit settings. During the sleep and standby modes, the CGRAM cannot be accessed.
R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
WD WD 15 14
WD WD 13 12
WD WD 11 10
WD WD WD WD WD WD WD WD WD WD 9 8 7 6 5 4 3 2 1 0
Figure 19 Write Data to CGRAM Instruction
36
HD66750/1
Read Data from CGRAM RD15-0 : Read 16-bit data from the CGRAM. When the data is read to the microcomputer, the first-word read immediately after the CGRAM address setting is latched from the CGRAM to the internal read-data latch. The data on the data bus (DB150) becomes invalid and the second-word read is normal. When bit processing, such as a logical operation, is performed within the HD66750/1, only one read can be processed since the latched data in the first word is used.
R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
1
RD 15
RD 14
RD 13
RD 12
RD 11
RD 10
RD 9
RD 8
RD 7
RD 6
RD 5
RD 4
RD 3
RD 2
RD 1
RD 0
Figure 20 Read Data from CGRAM Instruction
Sets the I/D and AM10 bits
Sets the I/D and AM10 bits
Address: N set
Address: N set
First word
Dummy read (invalid data) CGRAM -> Read-data latch
First word
Dummy read (invalid data) CGRAM -> Read-data latch
Second word
Read (data of address n) Read-data latch -> DB150
Second word
Read (data of address n) DB150 -> CGRAM
Address: M set
Automatic address update: M +
First word
Dummy read (invalid data) CGRAM -> Read-data latch
First word
Dummy read (invalid data) CGRAM -> Read-data latch
Second word
Read (data of address) Read-data latch -> DB150
Second word
Write (data of address n) DB150 -> CGRAM
i) Data read to the microcomputer
ii) Logical operation processing in the HD66750/1
Figure 21 CGRAM Read Sequence
37
Table 16 Instruction List
Reg. No. IR SR R00 Index Status read Start oscillation Device code read R01 Driver output control R02 LCD-drivingwaveform control R03 Power control 0 1 * * * BS2 BS1 BS0 BT1 BT0 * * 0 1 * * * * * * * * * Register Name R/W 0 1 0 1 0 Upper Code Lower Code Description Sets the index register value. Reads the driving raster-row position (L60) and contrast setting (C50). Starts the oscillation mode. Reads 0750H. Sets the common driver shift direction (CMS), segment driver shift direction (SGS), driving duty ratio (NL30), and centering (CN). B/C EOR NW4 NW3 NW2 NW1 NW0 Sets the LCD drive AC waveform (B/C), and EOR output (EOR) or the number of n-raster-rows (NW40) at C-pattern AC drive. DC1 DC0 AP1 AP0 SLP STB Sets the sleep mode (SLP), standby mode (STB), LCD power on (AP10), boosting cycle (DC10), boosting ouput multiplying factor (BT10), and LCD drive bias value (BS20). R04 R05 Contrast control Entry mode 0 0 1 1 * * * * * * * * * * * * * * * * * * * * CT5 CT4 CT3 CT2 CT1 CT0 Sets the contrast adjustment (CT50). * I/D AM1 AM0 LG1 LG0 Specifies the logical operation (LG10), AC counter mode (AM10), and increment/decrement mode (I/D). R06 R07 Rotation Display control 0 0 1 1 * * * * * * * * * * * * * * * * * * * * * * * RT2 RT1 RT0 Specifies the amount of write-data rotation (RT20). GS REV D Specifies display on (D), black-and-white reversed display (REV), grayscale mode (GS), double-height display on (DHE), and partial scroll (PS10). R08 R09 R0A R0B R0C R10 Cursor control Double-height display position Vertical scroll Horizontal cursor position Vertical cursor position RAM write data mask R11 R12 RAM address set RAM data write RAM data read Note: '*' means 'doesn't matter'. 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 * * * * * WM 15 * * * * * * * * * * * * * * * * * C CM1 CM0 Specifies cursor display on (C) and cursor display mode (CM10). 0 0 0 0 0 0 0 0 0 0 0 RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 * 0 * 0 * * L6 * 0 * * L5 * 0 * * L4 * 0 * * L3 * 0 * * L2 * 1 * * L1 * 1 * L0 * 1 * 0 * 0 * * 0 * 1 CN * C5 * 0 * ID4 C4 * 1 * ID3 C3 * 0 NL3 ID2 C2 * 0 NL2 ID1 C1 * 0 NL1 ID0 C0 1 0 NL0
Execution Cycle
0 0 10 ms 0 0
CMS SGS
PS1 PS0 DHE
DE6 DE5 DE4 DE3 DE2 DE1 DE0 * * * * * * *
DS6 DS5 DS4 DS3 DS2 DS1 DS0 Specifies double-height display start (DS60) and end (DE60). SL6 SL5 SL4 SL3 SL2 SL1 SL0 Sets the display-start raster-row (SL60).
HE6 HE5 HE4 HE3 HE2 HE1 HE0 VE6 VE5 VE4 VE3 VE2 VE1 VE0 WM 14 * WM
13
HS6 HS5 HS4 HS3 HS2 HS1 HS0 Sets horizontal cursor start (HS60) and end (HE60). VS6 VS5 VS4 VS3 VS2 VS1 VS0 Sets vertical cursor start (VS60) and end (VE60).
WM
12
WM
11
WM WM9 WM8 WM7 WM6 WM5 WM4 WM3 WM2 WM1 WM0 Specifies write data mask (WM150) at RAM write. 10 AD108 (upper) AD70 (lower) Write data (lower) Read data (lower) Initially sets the RAM address to the address counter (AC). Writes data to the RAM. Reads data from the RAM.
*
*
*
0 0 0
Write data (upper) Read data (upper)
HITACHI
38
HD66750/1
Reset Function
The HD66750/1 is internally initialized by RESET input. Because the busy flag (BF) indicates a busy state (BF = 1) during the reset period, no instruction or CGRAM data access from the MPU is accepted. The reset input must be held for at least 1 ms. Do not access the CGRAM or initially set the instructions until the R-C oscillation frequency is stable after power has been supplied (10 ms). Instruction Set Initialization: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. Start oscillation executed Driver output control (CN = 0, NL30 = 1111, SGS = 0, CMS = 0) B-pattern waveform AC drive (B/C = 0, ECR = 0, NW40 = 00000) Power control (DC10 = 00, AP10 = 00: LCD power off, SLP = 0: Sleep mode off, STB = 0: Standby mode off) 1/11 bias drive (BS20 = 000), Two-times boost (BT10 = 00), Weak contrast (CT50 = 000000) Entry mode set (I/D = 1: Increment by 1, AM10 = 00: Horizontal move, LG10 = 00: Replace mode) Rotation (RT20 = 000: No shift) Display control (DHE = 0: Double-height display off, REV = 0, GS = 0, D = 0: Display off, PS10 = 00: Partial scroll off) Cursor control (C = 0: Cursor display off, CM10 = 00: White blink cursor) Double-height display position (DS60 = 0000000, DE60 = 0000000) Vertical scroll control (SL60 = 0000000: First raster-row displayed at the top) Window cursor display position (HS60 = HE60 = VS60 = VE60 = 0000000) RAM write data mask (WM150 = 0000H: No mask) RAM address set (AD100 = 000H)
CGRAM Data Initialization: This is not automatically initialized by reset input but must be initialized by software while display is off (D = 0). Output Pin Initialization: 1. LCD driver output pins (SEG/COM): Outputs GND level 2. Booster output pins (VLOUT): Outputs Vcc level 3. Oscillator output pin (OSC2): Outputs oscillation signal
39
HD66750/1
Parallel Data Transfer
16-bit Bus Interface Setting the IM2-0 (interface mode) to the GND/GND level allows 68-system E-clock-synchronized 16-bit parallel data transfer. Setting the IM1/0 to the Vcc/GND level allows 80-system 16-bit parallel data transfer. When the number of buses or the mounting area is limited, use an 8-bit bus interface.
CSn* A1 H8/2245 HWR* (RD*) D15-D0 16
CS* RS WR* HD66750/1 (RD*) DB15-DB0
Figure 22 8-bit Bus Interface
Interface to 16-bit
Microcomputer
Setting the IM1/0 (interface mode) to the GND/Vcc level allows 68-system E-clock-synchronized 8-bit parallel data transfer using pins DB15-DB8. Setting the IM1/0 to the Vcc/Vcc level allows 80-system 8bit parallel data transfer. The 16-bit index register, instructions and RAM data are divided into eight upper/lower bits and the transfer starts from the upper eight bits. Fix unused pins DB7-DB0 to the Vcc or GND level.
CSn* A1 H8/2245 HWR* (RD*) D15-D8 8 8 GND
CS* RS WR* HD66750/1 (RD*) DB15-DB8 DB7-0
Figure 23
Interface to 8-bit
Microcomputer
Note: Transfer synchronization function for an 8-bit bus interface The HD66750/1 supports the transfer synchronization function which resets the upper/lower counter to count upper/lower 8-bit data transfer in the 8-bit bus interface. Noise causing transfer mismatch between the eight upper and lower bits can be corrected by a reset triggered by consecutively writing a 00H instruction four times. The next transfer starts from the upper eight bits. Executing synchronization function periodically can recover any runaway in the display system.
40
HD66750/1
RS
R/W E DB15 DB8 00H (1) 00H (2) 00H (3) 00H Upper (4) (8-bit transfer synchronization) Lower
Upper/ lower
Figure 24 8-bit Transfer Synchronization
41
HD66750/1
Graphics Operation Function
The HD66750/1 can greatly reduce the load of the microcomputer graphics software processing through the 16-bit bus architecture and graphics-bit operation function. This function supports the following: 1. A write data mask function that selectively rewrites some of the bits in the 16-bit write data. 2. A bit rotation function that shifts and writes the data sent from the microcomputer in a bit unit. 3. A logical operation function that writes the data sent from the microcomputer and the original RAM data by a logical operation. S inc e the displa y data in the gra phics R AM (C GR AM) ca n be quickly re written, the load of the microc ompute r proc essing ca n be re duce d in the lar ge displa y scr ee n whe n a font patter n, such as kanji characters, is developed for any position (BiTBLT processing). The gra phics bit oper ation ca n be contr olle d by combining the entr y mode re giste r, the bit set value of the RAM-write-data mask register, and the read/write from the microcomputer. Table 17 Graphics Operation
Bit Setting Operation Mode Write mode 1 Write mode 2 Write mode 3 Read/write mode 1 Read/write mode 2 Read/write mode 3 I/D 0/1 0/1 0/1 0/1 0/1 0/1 AM 00 01 10 00 01 10 LG 00 00 00 01 10 11 01 10 11 01 10 11 Operation and Usage Horizontal data replacement, horizontal-border drawing Vertical data replacement, font development, verticalborder drawing Vertical data replacement with two-word width, kanjifont development Horizontal data replacement with logical operation, horizontal-border drawing Vertical data replacement with logical operation, vertical-border drawing Horizontal data replacement with two-word-width logical operation
42
HD66750/1
Microcomputer
16
16
HD66750/1
+1/1 Readdata latch +16 16 Address counter (AC) 16 2 Logical operation 16 16 Write bit mask 11 Bit rotation Write-data latch 16 3 Rotation bit (RT20) Logical operation bit (LG10) 00: through 01: OR 10: AND 11: EOR
Write-mask register (WM150)
Graphics RAM (CGRAM)
Figure 25 Data Processing Flow of the Graphics Bit Operation 1. Write mode 1: AM10 = 00, LG10 = 00 This mode is used when the data is horizontally written at high speed. It can also be used to initialize the gra phics R AM (C GR AM) or to dra w borde rs. The rota tion func tion (R T20) or wr ite -data mask func tion (W M150) ar e also ena bled in these oper ations. Af te r wr iting, the addr ess counte r (A C) automatica lly incr ements by 1 (I /D = 1) or dec re me nts by 1 (I /D = 0), and automatica lly jumps to the counter edge one-raster-row below after it has reached the left edge of the graphics RAM.
43
HD66750/1
Operation Examples: 1) I/D = 1, AM10 = 00, LG10 = 00, RT20 = 000 2) WM150 = 0000H 3) AC = 000H
WM0 Write data mask:
WM15
00 00 00 00 00 00 00 00 DB0 DB15
Write data (1) : Write data (2) : Write data (3) :
10 0 110 0 10 100 00 1 1 11 00 00 1 100 00 1 100 01 1 10 100 00 0 11 11 1
000H
001H
002H
01 1 10 100 00 0 11 11 1 Write data (3)
1 00 11 00 10 10 00 01 1 11 00 00 1 100 00 1 100 Write data (1) Write data (2)
CGRAM
Figure 26 Writing Operation of Write Mode 1 2. Write mode 2: AM10 = 01, LG10 = 00 This mode is used whe n the data is ver tic ally wr itten at high spee d. It ca n also be used to initia liz e the gra phics R AM (C GR AM), deve lop the font patter n in the ver tic al dire ction, or dra w borde rs. The rotation function (RT20) or write-data mask function (WM150) are also enabled in these operations. After writing, the address counter (AC) automatically increments by 16, and automatically jumps to the upper-right edge (I/D = 1) or upper-left edge (I/D = 0) following the I/D bit after it has reached the lower edge of the graphics RAM.
Operation Examples: 1) I/D = 1, AM10 = 01, LG10 = 00, RT20 = 010 2) WM150 = F007H 3) AC = 000H WM0 WM15
Write data mask: 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 DB0 DB15 4-bit rotation 4-bit rotation 4-bit rotation
Write data (1) : 1 0 0 1 1 0 0 1 0 1 0 0 0 0 1 1 Write data (2) : 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 Write data (3) : 0 1 1 1 0 1 0 0 0 0 0 1 1 1 1 1
00 1 110 0 110 0 10 100 1 100 11 00 00 1 100 00 1 11 101 1 10 100 00 0 1
000H 010H 020H
* * * 11 00 11 00 1 * * * * * * * 011 0 00 01 1 * * * * * * * 101 1 10 10 0 * * * *
Write data (1) Write data (2) Write data (3)
CGRAM
Notes: 1. The bit area data in the RAM indicated by '*' is not changed. 2. After writing to address 7F0H, the AC jumps to 001H.
Figure 27 Writing Operation of Write Mode 2
44
HD66750/1
3. Write mode 3: AM10 = 10, LG10 = 00 This mode is used when the data is written at high speed by vertically shifting bits. It can also be used to wr ite the 16-bit data for two wor ds into the gra phics R AM (C GR AM), deve lop the font patter n, or transfer the BiTBLT as a bit unit. The rotation function (RT20) or write-data mask function (WM150) ar e also ena bled in these oper ation. Howe ver , although the wr ite -data mask func tion masks the bit position set with the wr ite -data mask re giste r (W M150) at the odd-times (suc h as the first or third) wr ite , the func tion masks the bit position that re ver se d the setting value of the wr ite -data mask re giste r (W M150) at the eve n-times (suc h as the sec ond or four th) wr ite . Af ter the odd-times wr iting, the addr ess counte r (A C) automatica lly incr ements by 1 (I /D = 1) or dec re me nts by 1 (I /D = 0). Af te r the even-times writing, the AC automatically increments or decrements by 1 + 16 (I/D = 1) or +1 + 16 (I/D = 0). The AC automatically jumps to the upper edge after it has reached the lower edge of the graphics RAM.
Operation Examples: 1) I/D = 1, AM10 = 10, LG10 = 00, RT20 = 010 2) WM150 = 0007H 3) AC = 000H
WM0 Write data mask:
WM15
11 1 100 00 00 00 0 00 0 DB0 DB15 4-bit rotation 4-bit rotation 4-bit rotation 4-bit rotation 4-bit rotation 4-bit rotation
Write data (1) : Write data (2) : Write data (3) : Write data (4) : Write data (5) : Write data (6) :
11 1 111 0 00 001 10 0 0 11 11 11 0 000 01 1 000 00 0 00 111 00 0 01 11 1 00 0 00 111 00 0 01 11 1 00 1 00 00 11 11 11 00 0 00 1 00 00 11 11 11 00 0
10 0 011 1 111 0 00 001 1 000 11 11 11 0 000 01 1 11 100 0 00 111 00 0 0 1 11 100 0 00 111 00 0 0 1 00 000 1 00 00 11 11 1 1 00 000 1 00 00 11 11 1
000H 000H 010H 020H
001H
* * * * 1 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 * * * * * * * * * * * * Write data (1), (2) * * * * 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 * * * * * * * * * * * * Write data (3), (4) * * * * 0 0 1 0 0 0 0 1 1 1 1 1 1 0 0 0 * * * * * * * * * * * * Write data (5), (6)
7F0H
Notes: 1. The bit area data in the RAM indicated by '*' is not changed. 2. After writing to address 7F0H, the AC jumps to 001H.
CGRAM
Figure 28 Writing Operation of Write Mode 3
45
HD66750/1
4. Read/Write mode 1: AM10 = 00, LG10 = 01/10/11 This mode is used when the data is horizontally written at high speed by performing a logical operation with the original data . It re ads the displa y data (or igina l data ), which has alr eady bee n wr itten in the gra phics R AM (C GR AM), per forms a logical oper ation with the wr ite data sent fr om the microcomputer, and rewrites the data to the CGRAM. This mode can read the data during the same bus cycle as for the write operation since the read operation of the original data does not latch the read data into the microcomputer and temporarily holds it in the read-data latch. The rotation function (RT20) or wr ite -data mask func tion (W M150) ar e also ena bled in these oper ations. Af te r wr iting, the addr ess counte r (A C) automatica lly incr ements by 1 (I /D = 1) or dec re ments by 1 (I /D = 0), and automatica lly jumps to the counter edge one-raster-row below after it has reached the left or right edges of the graphics RAM.
Operation Examples: 1) I/D = 1, AM10 = 00, LG10 = 01 (OR), RT20 = 000 2) WM150 = 0000H 3) AC = 000H WM0 Write data mask: WM15
00 00 00 00 00 00 00 00 DB0 DB15 Logical operation (OR) 10 1 111 0 10 110 00 1 1 Logical operation (OR) 11 00 11 1 110 00 1 100 Logical operation (OR) 01 1 11 110 10 0 11 11 1
Read data (1): Write data (1): Read data (2): Write data (2): Read data (3): Write data (3):
10 0 110 0 10 100 00 1 1 10 1 111 0 00 110 00 0 1 00 00 11 1 100 00 0 000 11 00 00 1 110 00 1 100 00 0 01 110 10 0 00 11 0 01 1 10 100 00 0 11 11 1
000H
10 1 111 0 10 11 00 01 1
001H
11 001 1 1 110 00 1 100
002H
01 1 11 11 0 100 11 11 1
Read data (1) + Write data (1) Read data (2) + Write data (2) Read data (3) + Write data (3)
CGRAM
Figure 29 Writing Operation of Read/Write Mode 1 5. Read/Write mode 2: AM10 = 01, LG10 = 01/10/11 This mode is used whe n the data is ver tic ally wr itten at high spee d by per forming a logical oper ation with the original data . It re ads the displa y data (or igina l data ), which has alr eady bee n wr itten in the gra phics R AM (C GR AM), per forms a logical oper ation with the wr ite data sent fr om the microcomputer, and rewrites the data to the CGRAM. This mode can read the data during the same bus cycle as for the write operation since the read operation of the original data does not latch the read data into the microcomputer and temporarily holds it in the read-data latch. The rotation function (RT20) or wr ite -data mask func tion (W M150) ar e also ena bled in these oper ations. Af te r wr iting, the addr ess counter (AC) automatically increments by 16, and automatically jumps to the upper-right edge (I/D = 1) or upper -lef t edge (I /D = 0) following the I/D bit af ter it has re ac hed the lower edge of the gra phics RAM.
46
HD66750/1
Operation Examples: 1) I/D = 1, AM10 = 01, LG10 = 01 (OR), RT20 = 010 2) WM150 = FC03H 3) AC = 000H WM0 Write data mask: WM15
11 00 00 00 00 1 11 11 1 DB0 DB15 4-bit rotation 10 1 111 0 00 110 00 0 1 00 0 110 1 111 0 00 110 Logical operation (OR) 10 01 10 11 1 100 01 1 1
Read data (1): Write data (1):
10 0 110 0 10 100 00 1 1
Read data (2): Write data (2):
00 00 11 1 100 00 0 000 4-bit rotation 11 00 00 1 110 00 1 100 1 100 11 00 00 1 110 00 Logical operation (OR) 11 001 11 100 11 10 00
Read data (3): Write data (3):
00 0 01 110 1 11 00 11 0 4-bit rotation 01 1 10 100 00 0 11 11 1 1 11 101 1 10 100 00 0 1 Logical operation (OR) 11 111 1 11 1 110 0 111
000H 000H 010H 020H
001H
* * 0 1 1 0 1 1 1 1 * * * * * * Read data (1) + Write data (1) * * 0 0 1 1 1 1 0 0 * * * * * * Read data (2) + Write data (2) * * 1 1 1 1 1 1 1 1 * * * * * * Read data (3) + Write data (3)
CGRAM
7F0H
Notes: 1. The bit area data in the RAM indicated by '*' is not changed. 2. After writing to address 7F0H, the AC jumps to 001H.
Figure 30 Writing Operation of Read/Write Mode 2 6. Read/Write mode 3: AM10 = 10, LG10 = 01/10/11 This mode is used when the data is written with high speed by vertically shifting bits and by performing logical operation with the original data. It can be also used to write the 16-bit data for two words into the graphics RAM (CGRAM), develop the font pattern, or transfer the BiTBLT as a bit unit. This mode can read the data during the same bus cycle as for the write operation since the read operation of the original data does not latch the read data into the microcomputer and temporarily holds it in the read-data latch. The rota tion func tion (R T20) or wr ite -data mask func tion (W M150) ar e also ena bled in these oper ations. Howe ver, although the wr ite -data mask func tion masks the bit position set with the wr ite data mask register (WM150) at the odd-times (such as the first or third) write, the function masks the bit position which re ver se d the setting value of the wr ite -data mask re giste r (W M150) at the eve n-times (suc h as the sec ond or four th) wr ite . Af te r the odd-times wr iting, the addr ess counte r (A C) automatically increments by 1 (I/D = 1) or decrements by 1 (I/D = 0). After the even-times writing, the AC automatica lly incr ements or dec re me nts by 1 + 16 (I /D = 1) or + 1 + 16 (I /D = 0). The AC automatically jumps to the upper edge after it has reached the lower edge of the graphics RAM.
47
HD66750/1
Operation Examples: 1) I/D = 1, AM10 = 10, LG10 = 01, RT20 = 010 2) WM150 = 000FH 3) AC = 000H WM0 Write data mask: WM15 11 1 100 00 00 00 0 00 0 DB0 Read data (1): Write data (1): DB15 4-bit rotation
00 0 111 1 00 00 01 10 0 11 1 111 0 00 001 10 0 0 10 0 011 1 111 0 00 001
Logical operation (OR) 10 0 111 1 111 0 01 101 Read data (2): Write data (2): 00 1 111 1 100 0 00 11 1 11 11 11 0 000 01 1 000 4-bit rotation 1 000 11 11 11 0 000 01
Logical operation (OR) 1 011 11 11 11 0 001 11 Read data (3): Write data (3): 00 1 10 011 00 0 00 11 0 00 0 00 111 00 0 01 11 1 4-bit rotation 1 11 100 0 00 111 00 0 0
Logical operation (OR) 1 11 100 1 10 111 01 1 0 Read data (4): Write data (4): 11 1 10 00 000 0 00 10 1 00 0 00 111 00 0 01 11 1 4-bit rotation 1 11 100 0 00 111 00 0 0
Logical operation (OR) 1 11 100 0 00 111 01 0 1
000H 000H 010H
001H
* * * * 1 1 1 1 1 1 0 0 1 1 0 1 1 0 1 1 * * * * * * * * * * * * Write data (1), (2) * * * * 0 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 * * * * * * * * * * * * Write data (3), (4)
7F0H
Notes: 1. The bit area data in the RAM indicated by '*' is not changed. 2. After writing to address 7F0H, the AC jumps to 001H.
CGRAM
Figure 31 Writing Operation of Read/Write Mode 3
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HD66750/1
Oscillation Circuit
The HD66750/1 can either be supplied with operating pulses externally (external clock mode) or oscillate using an internal R-C oscillator with an external oscillator-resistor (external resistor oscillation mode). Note that in R-C oscillation, the oscillation frequency is changed according to the internal capacitance value, the external resistance value, or operating power-supply voltage.
1) External clock mode 2) External resistor oscillation mode The oscillator frequency can be OSC1 Clock (70 kHz) OSC1 Rf OSC2 HD66750/1 adjusted by oscillator resistor (Rf). If Rf is increased or power supply voltage is decreased, the oscillation frequency decreases. For the relationship between Rf resistor value and oscillation frequency, see the Electric Characteristics Notes section.
HD66750/1 Dumping resistance (1.5 k)
Figure 32 Oscillation Circuits Table 18
LCD Duty 1/16 1/24 1/32 1/40 1/48 1/56 1/64 1/72 1/80 1/88 1/96 1/104 1/112 1/120 1/128
Relationship between Liquid Crystal Drive Duty Ratio and Frame Frequency
NL30 Set Value 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Recommended Drive Bias Value 1/6 1/6 1/6 1/7 1/8 1/8 1/9 1/9.5 1/10 1/10 1/10 1/11 1/11 1/11 1/11 Frame Frequency 70 Hz 70 Hz 70 Hz 69 Hz 71 Hz 71 Hz 70 Hz 71 Hz 69 Hz 68 Hz 68 Hz 69 Hz 71 Hz 67 Hz 70 Hz One-frame Clock 1024 1032 1024 1040 1008 1008 1024 1008 1040 1056 1056 1040 1008 1080 1024
Note: The frame frequency above is for 72-kHz operation and proportions the oscillation frequency (fosc).
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HD66750/1
1 V1 V2 COM1 V5 GND V1 V2 COM2 V5 GND V1 V2 COM127 V5 GND V1 V2 COM128 V5 GND 1 frame 1 frame 2 3 4 127 128 1 2 3 127 128
Figure 33 LCD Drive Output Waveform (B-pattern AC Drive with 1/128 Multiplexing Duty Ratio)
50
HD66750/1
n-raster-row Reversed AC Drive
The HD66750/1 supports not only the LCD reversed AC drive in a one-frame unit (B-pattern waveform) but also the n-raster-row reversed AC drive which alternates in an n-raster-row unit from one to 32 rasterrows (C-pattern waveform). When a problem affecting display quality occurs, such as crosstalk at highduty driving of more than 1/64 duty, the n-raster-row reversed AC drive (C-pattern waveform) can improve the quality. Determine the number of raster-rows n (NW bit set value + 1) for alternating after confirmation of the display quality with the actual LCD panel. However, if the number of AC raster-rows is reduced, the LCD alternating frequency becomes high. Because of this, the charge or discharge current is increased in the LCD cells.
1 frame 1 frame
1 2 3 4 5 6 7 8 9 10 11 12 13
79 80 1 2 3 4 5 6 7 8 9 10 1112 13
79 80 1 2 3
B-pattern waveform drive 1/80 duty C-pattern waveform drive 1/80 duty 11-raster-row reversal Without EORs C-pattern waveform drive 1/80 duty 11-raster-row reversal With EORs Note: Specify the number of AC drive raster-rows and the necessity of EOR so that the DC bias is not generated for the liquid crystal.
Figure 34 Example of an AC Signal under n-raster-row Reversed AC Drive
51
HD66750/1
Liquid Crystal Display Voltage Generator
When External Power Supply and Internal Operational Amplifiers are Used To supply LCD drive voltage directly from the external power supply without using the internal booster, circuits should be connected as shown in figure 35. Here, contrast can be adjusted by software through the CT bits of the contrast adjustment register. The HD66750/1 incorporates a voltage-follower operational amplifier for each V1 to V5 to reduce current flowing through the internal bleeder-resistors, which generate different levels of liquid-crystal drive voltages. Thus, potential difference between VLCD and V1 must be 0.1 V or higher, and that between V4 and GND must be 1.4 V or higher. Note that the OPOFF pin must be grounded when using the operational amplifiers. Place a capacitor of about 0.47 F (B characteristics) between each internal operational amplifier (V1OUT to V5OUT outputs) and GND and stabilize the output level of the operational amplifier. Adjust the capacitance value of the stabilized capacitor after the LCD panel has been mounted and the screen quality has been confirmed.
52
HD66750/1
O POFF = G ND VLCD
V LCD VR V 1OUT R V 2OUT R0 V 3OUT R 0.47 F* (B characteristics) V 5OUT V 4OUT R
+ + + + + -
HD66750/1
V1
V2 LCD driver V3 V4
SEG1 to SEG128
CO M1 to CO M12
V5
G ND
GND V ci C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5C6+ C6V LOUT
R GND
B ooster
Note: A djust the capacitance value of the capacitor after the LCD p anel has b een mounted. The capacitors connected to V 1OUT to V 5OUT/GND should b e more the V lcd voltage. The voltage of these capacitors should b e determined with fluctuation of voltage.
Figure 35 External Power Supply Circuit for LCD Drive Voltage Generation When an Internal Booster and Internal Operational Amplifiers are Used To supply LCD drive voltage using the internal booster, circuits should be connected as shown in figure 36. Here, contrast can be adjusted through the CT bits of the contrast control instruction. Temperature can be compensated either through the CT bits or by controlling the reference voltage for the booster (Vci pin) using a thermistor. Note that Vci is both a reference voltage and power supply for the booster. The reference voltage must therefore be adjusted using an emitter-follower or a similar element so that sufficient current can be supplied. In this case, Vci must be equal to or smaller than the VCC level.
53
HD66750/1
The HD66750/1 incorporates a voltage-follower operational amplifier for each of V1 to V5 to reduce current flowing through the internal bleeder-resistors, which generate different liquid-crystal drive voltages. Thus, potential difference between VLCD and V1 must be 0.1 V or higher, and that between V4 and GND must be 1.4 V or higher. Note that the OPOFF pin must be grounded when using the operational amplifiers. Place a capacitor of about 0.47 F (B characteristics) between each internal operational amplifier (V1OUT to V5OUT outputs) and GND and stabilize the output level of the operational amplifier. Adjust the capacitance value of the stabilized capacitor after the LCD panel has been mounted and the screen quality has been confirmed.
54
HD66750/1
O PO FF = G ND
VLCD VR V1OUT R V2OUT R0 V3OUT R 0.47 F* (B characteristics ) V5OUT V4OUT R
+ + + + + -
HD6 6750/1
V1
V2 LCD driver V3 V4
SEG1 to SEG128
CO M 1 to CO M128
V5
GN D Vci
1 F (+)
(B Characteris tics )
GND Vci C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5C6+ C6VLOU T
R GND
1 F (+)
(B Characteris tic s)
1 F (+)
(B Characteris tics )
B oo ste r
1 F (+)
(B Charac teristic s)
1 F (+)
(B Charac teristic s)
1 F (+) 1 F
(B Characteris tics )
(+ )
(B Charac teristic s)
GND Not es : 1. The reference voltage input (Vci) mus t be adjus ted s o that the outp ut voltage after boos ting will not exc the ab solute maximum rating f or the liquid-crystal power s up ply v oltage (16.5 V) . 2. Vci is both a reference v oltage and p ow er supp ly for the boost er; connect it to Vcc directly or comb ine it with a t rans istor so t hat suff icient current can b e obt ained. 3. Polariz ed capacitors m us t be connected corr ctly. e 4. Circuits for temp erature comp ensat ion s hould b e b as ed on the sampl e circ uits in figure 37. 5. Adjust the capacitance value of the stab ilized capacitor aft er the LCD panel has been m ounted. 6. The cap acitors connected to C3+/ C3 and C 6+ /C 6 should three times or more the Vci v oltage. 7. The cap acitors connected to C1+/ C1, C2+/ C2, C 4+ /C 4 and C5+/ C5 s hould b e more the V ci volta 8. The cap acitors connected to VLOU T/GND and V 1OU T to V5OUT/ GND should be more the N times Vci v oltage. (N: b oost ing factor) 9. The v oltage of these capacitors should be determi ned with fluctuation of voltage.
Figure 36 Internal Booster for LCD Drive Voltage Generation
55
HD66750/1
HD66750/1 V cc V cc 1 F (B characteristics)
(+)
HD66750/1 V cc
Thermistor
Tr
V ci
GND Thermistor Tr
V ci
GND (Examp le 1)
GND (Examp le 2)
Figure 37 Temperature Compensation Circuits Switching the Boosting Factor Instruction bits (BT1/0 bits) can optionally select the boosting factor of the internal booster. According to the display status, power consumption can be reduced by changing the LCD drive duty and the LCD drive bias, and by controlling the boosting factor for the minimum requirements. For details, see the Partialdisplay-on Function section. Because of the maximum boosting factor, external capacitors need to be connected. For example, when the maximum boosting is six times or five times, capacitors between C6+ and C6 or between C5+ and C5 are needed as well, as in the case of the seven-times boosting. When the boosting is two-times boosting, capacitors between C1+ and C1 or between C4+ and C4 are not needed. Place a capacitor with a voltage of three times or more the Vci-GND voltage between C6+ and C6 and between C3+ and C3, and a capacitor with a voltage larger than the Vci-GND voltage between C1+ and C1, C2+ and C2, C4+ and C4, and C5+ and C5. Place a capacitor with a voltage of N times theVci-GND voltage between VLOUT and GND. (N: boosting factor) Note that each capacitors with a voltage should be determined with a voltage fluctuation. Table 19
BT1 0 0 1 1
VLOUT Output Status
BT0 0 1 0 1 VLOUT Output Status Two-times boosting output Five-times boosting output Six-times boosting output Seven-times boosting output
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HD66750/1
i) Maximum seven-times boosting Vci
1 F
(+)
(B Characteristics)
ii) Maximum six-times boosting Vci
1 F 1 F
(+)
(B Characteristics)
Vci C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5C6+ C6(+)
Vci C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5C6+ C6(+)
1 F (+)
(B Characteristics)
(+)
(B Characteristics)
1 F 1 F
(+)
1 F (+)
(B Characteristics)
(B Characteristics)
(+)
1 F (+)
(B Characteristics)
(B Characteristics)
1 F (+)
(B Characteristics)
1 F
(+)
(B Characteristics)
1 F
(+)
1 F (+)
(B Characteristics)
(B Characteristics)
1 F
(B Characteristics)
VLOUT
1 F
(B Characteristics)
VLOUT
GND
GND
iii) Maximum five-times boosting Vci
1 F
(+)
(B Characteristics)
iv) Maximum two-times boosting Vci
Vci C1+ C11 F (+)
(B Characteristics)
Vci C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5C6+ C6(+)
1 F (+)
(B Characteristics)
C2+ C2C3+ C3C4+ C4-
1 F 1 F
(+)
1 F
(+)
(B Characteristics)
(B Characteristics)
(+)
(B Characteristics)
1 F (+)
(B Characteristics)
1 F (+)
(B Characteristics)
C5+ C5C6+ C6(+)
1 F
(+)
1 F
(+)
(B Characteristics)
(B Characteristics)
1 F
(B Characteristics)
VLOUT
1 F
(B Characteristics)
VLOUT
GND
GND
Figure 38 Booster Output Factor Switching
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HD66750/1
Example of Power-supply Voltage Generator for More Than Seven-times Boosting Output The HD66750/1 incorporates a booster for up to seven-times boosting. However, the LCD drive voltage (VLCD) will not be enough for seven-times boosting from Vcc when the power-supply voltage of Vcc is low or when the LCD drive voltage is high for the high-contrast LCD display. In this case, the reference voltage (Vci) for boosting can be set higher than the power-supply voltage of Vcc. When the boosting factor is high, the current driving ability is lowered and insufficient display quality may result. In this case, the boosting ability can be improved by decreasing the boosting factor as shown in the booster in figure 39. Set the Vci input voltage for the booster to 3.6 V or less within the range of Vcc + 1.0 V. Control the Vci voltage so that the boosting output voltage (VLOUT) should be less than the absolute maximum ratings (16.5 V).
HD66750/ 1
Regulator (1)
1.8 V
Vci Vcc
L ogic circuit
B attery 3.6 V
C1+ Regulator (2)
( +)
1 F
(B Characteri s tics )
2.2 V
Vci
C1 C2+
( +)
1 F
(B Chara cteristic s)
B ooster
GND VLCD (= 15.4 V)
C2 C3+ C3 C4+ C4
( +)
1 F
(B Chara cteristic s)
( +)
1 F
(B Ch aracteristi cs)
2.2 V x 7 = 15.4 V
C5+ VLOUT C5 C6+ C6
( +)
1 F
(B Ch aracteristi cs)
( +)
1 F
(B Ch aracteristi cs)
GND 1 F
(B Characteri s tics )
( +)
VLCD
LCD driver
GND
SEG1 to SEG128 COM1 t o COM128
Vci (= 2. 2 V) Vcc (= 1. 8 V) GND (= 0 V) Note: I n pract ice, t he LCD drive cur rent lower s t he volt age in t he boost ing out put volt age.
GND
Figure 39 Usage Example of Booster at Vci > Vcc
58
HD66750/1
Contrast Adjuster
Software can adjust 64-step contrast for an LCD by varying the liquid-crystal drive voltage (potential difference between VLCD and V1) through the CT bits of the contrast adjustment register (electron volume function). The value of a variable resistor between VLCD and V1 (VR) can be precisely adjusted in a 0.05 x R unit within a range from 0.05 x R through 3.20 x R, where R is a reference resistance obtained by dividing the total resistance. The HD66750/1 incorporates a voltage-follower operational amplifier for each of V1 to V5 to reduce current flowing through the internal bleeder resistors, which generate different liquid-crystal drive voltages. Thus, CT5-0 bits must be adjusted so that potential difference between VLCD and V1 is 0.1 V or higher and that between V4 and GND is 1.4 V or higher when liquid-crystal drives, particularly when the VR is small.
HD66750/1
VLCD VR R R R0 R R GND + + V4 V5 GND + + + CT V1 V2 V3
Figure 40 Contrast Adjuster
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HD66750/1
Table 20 Contrast Adjustment Bits (CT) and Variable Resistor Values
CT Set Value
CT5 CT4 CT3 CT2 CT1 CT0
Variable Resistor Potential Difference between V1 and GND Value (VR) 3.20 x R 3.15 x R 3.10 x R 3.05 x R 3.00 x R 2.95 x R 2.90 x R 2.85 x R 2.80 x R 2.75 x R 2.70 x R 2.65 x R 2.60 x R
Display Color
0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1
0 0 1 1 0 0 1 1 0 0 1 1 0
0 1 0 1 0 1 0 1 0 1 0 1 0
(Small)
(Light)
0 1 1 1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0 0 1 1
1 0 0 0 0 1 1 1 1 0 0
1 0 0 1 1 0 0 1 1 0 0
1 0 1 0 1 0 1 0 1 0 1
1.65 x R 1.60 x R 1.55 x R 1.50 x R 1.45 x R 1.40 x R 1.35 x R 1.30 x R 1.25 x R 1.20 x R 1.15x R
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
0 0 1 1
0 1 0 1
0.20 x R 0.15 x R 0.10 x R 0.05 x R
(Large)
(Deep)
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HD66750/1
Liquid-crystal-display Drive-bias Selector
An optimum liquid-crystal-display bias value can be selected using the BS2-0 bits, according to the liquid crystal drive duty ratio setting (NL3-0 bits). The liquid-crystal-display drive duty ratio and bias value can be displayed while switching software applications to match the LCD panel display status. The optimum bias value calculated using the following expression is a logical optimum value. Driving by using a lower value than the optimum bias value provides lower logical contrast and lower liquid-crystal-display voltage (the potential difference between V1 and GND), which results in better image quality. When the liquidcrystal-display voltage is insufficient even if a seven-times booster is used, when the boosting driving ability is lowered by setting a high factor for the booster, or when the output voltage is lowered because the battery life has been reached, the display can be made easier to see by lowering the liquid-crystal-display bias. The liquid crystal display can be adjusted by using the contrast adjustment register (CT5-0 bits) and selecting the booster output level (BT1/0 bits). Optimum bias value for 1/N duty ratio drive voltage = Table 21
LCD drive duty ratio (NL3-0 set value) Optimum drive bias value (BS2-0 set value)
1 N+1
Optimum Drive Bias Values
1/128 1111 1/11 1/120 1110 1/11 1/112 1101 1/11 1/104 1100 1/11 1/96 1011 1/10 1/88 1010 1/10 1/80 1001 1/10 1/72 1000 1/9 1/64 0111 1/9 1/32 0100 1/6 1/24 0011 1/6 1/16 0010 1/5
000
000
000
000
001
001
001
010
010
101
101
100
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HD66750/1
VLC D VLCD VLCD VLCD VLCD
VR V1 R V2 R V3 7R V4 R V5 R GND GND i) 1/ 11 bias (BS20 = 000) VLCD
VR V1 R V2 R V3 6R R V5 R GND GN D ii) 1/ 10 bias (BS20 = 001) VLCD
VR V1 R V2 R V3 5R V4 R V5 R GND GND iii) 1/ 9 bias (BS20 = 010) V4
VR V1 R V2 R V3 4R R V5 R GN D GND iv) 1/ 8 bias (BS20 = 011)
VR V1 R V2 R V3 3R V4 R V5 R GND GND v) 1/7 bias (BS20 = 100) V4
VLCD VR V1 R V2 R V3 2R V4 R V5 R GND GND v) 1/6 bias (BS20 = 101) GND v) 1/5 bias (BS20 = 110) R GND GND vi) 1/ 4 bias (BS20 = 111) R V5 R GND R V4 R V5 N ote: R = Reference resistor R V3 R R V2 R V2 V3,V4 VR V1 VR V1
Figure 41 Liquid Crystal Display Drive Bias Circuit
62
HD66750/1
Table 22
Bias
Contrast Adjustment per Bias Drive Voltage
LCD drive voltage: VDR
- LCD drive voltage adjustment range
Contrast adjustment range : 0.775 x (VLCD-GND) VDR 0.995 x (VLCD-GND)
1/11 bias drive
11 x R x (VLCD - GND) 11 x R + VR
2xR - Limit of potential x (VLCD-GND) 1.4 [V] : 11 x R + VR difference between V4 and GND VR - Limit if potential x (VLCD-GND) 0.1 [V] : difference between VLCD and V1 11 x R + VR
- LCD drive voltage adjustment range
: 0.757 x (VLCD-GND) VDR 0.995 x (VLCD-GND)
1/10 bias drive
10 x R x (VLCD - GND) 10 x R + VR
2xR - Limit of potential x (VLCD-GND) 1.4 [V] : difference between V4 and GND 10 x R + VR VR - Limit if potential x (VLCD-GND) 0.1 [V] : difference between VLCD and V1 10 x R + VR
- LCD drive voltage adjustment range
: 0.737 x (VLCD-GND) VDR 0.994 x (VLCD-GND) x (VLCD-GND) 1.4 [V] x (VLCD-GND) 0.1 [V]
1/9 bias drive
9xR 9 x R + VR
x (VLCD - GND)
2xR - Limit of potential : 9 x R + VR difference between V4 and GND VR - Limit if potential : difference between VLCD and V1 9 x R + VR
- LCD drive voltage adjustment range
: 0.714 x (VLCD-GND) VDR 0.993 x (VLCD-GND) 2xR x (VLCD-GND) 1.4 [V] 8 x R + VR VR x (VLCD-GND) 0.1 [V] 8 x R + VR
1/8 bias drive
8xR x (VLCD - GND) 8 x R + VR
- Limit of potential : difference between V4 and GND
1/7 bias drive
- Limit if potential : difference between VLCD and V1 - LCD drive voltage : 0.686 x (VLCD-GND) VDR 0.993 x (VLCD-GND) adjustment range
7xR x (VLCD - GND) 7 x R + VR
2xR - Limit of potential x (VLCD-GND) 1.4 [V] : 7 x R + VR difference between V4 and GND VR - Limit if potential x (VLCD-GND) 0.1 [V] : difference between VLCD and V1 7 x R + VR
- LCD drive voltage adjustment range
: 0.652 x (VLCD-GND) VDR 0.992 x (VLCD-GND) 2xR x (VLCD-GND) 1.4 [V] 6 x R + VR VR x (VLCD-GND) 0.1 [V] 6 x R + VR
1/6 bias drive
6xR x (VLCD - GND) 6 x R + VR
- Limit of potential : difference between V4 and GND
1/5 bias drive
- Limit if potential : difference between VLCD and V1 - LCD drive voltage : 0.610 x (VLCD-GND ) VDR 0.990 x (VLCD-GND) adjustment range
5xR - Limit of potential : x (VLCD - GND) difference between V4 and GND 5 x R + VR
- Limit if potential : difference between VLCD and V1 - LCD drive voltage adjustment range
2xR x (VLCD-GND ) 1.4 [V] 5 x R + VR VR x (VLCD-GND ) 0.1 [V] 5 x R + VR
1/4 bias drive
: 0.556 x (VLCD-GND) VDR 0.988 x (VLCD-GND) 2xR x (VLCD-GND) 1.4 [V] 4 x R + VR VR x (VLCD-GND) 0.1 [V] 4 x R + VR
4xR x (VLCD - GND) 4 x R + VR
- Limit of potential : difference between V4 and GND - Limit if potential : difference between VLCD and V1
63
HD66750/1
Four-grayscale Display Function
The HD66750/1 supports the four-grayscale monochrome display function. The four-grayscale monochrome display is used for the display data of the two-bit pixel set sent to the CGRAM. There are four grayscale levels: always unlit, weak middle level, strong middle level, and always lit. In the weak middle-level grayscale display, the GS bit can select the 1/3 or 1/2 level. The frame rate control (FRC) method is used for grayscale control. Table 23
Upper Bit 0 0
Relationships between the CGRAM Data and the Display Contents
Lower Bit 0 1 Liquid Crystal Display Non-selected (unlit) GS = 0: 1/3-level grayscale (one frame lit during a three-frame period) GS = 1: 1/2-level grayscale (one frame lit during a two-frame period)
1 1 Note:
0 1
2/3-level grayscale (two frames lit during a three-frame period) Selected (lit)
Upper bits: DB15, DB13, DB11, DB9, DB7, DB5, DB3, and DB1 Lower bits: DB14, DB12, DB10, DB8, DB6, DB4, DB2, and DB0
L SB DB0
MSB LSB DB15 DB0
MSB DB15
0 010 011 111 011000
0000101001011111
CGRAM
Grayscal e c ontrol circuit
LCD panel display
Figure 42 Four-grayscale Monochrome Display
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Window Cursor Display Function
The HD66750/1 displays the window cursor by specifying a window area. The horizontal display position of the window cursor is specified with the horizontal cursor position register (HS60 to HE60), and the vertical display position is specified with the vertical cursor position register (VS60 or VE60). In these display position setting registers, ensure that HS60 HE60 and VS60 VE60. If these relationships are not satisfied, normal display cannot be attained. In addition, if the setting is VS60 = VE60 = 00H, a cursor is displayed on a raster-row at the most-upper edge of the screen. This window cursor can automatically display the hardware-supported block cursor, highlight window, or menu bar. The CM10 bits select the following four displays in each window cursor: 1. White-blink cursor (CM10 = 00): Alternately blinks between the normal display and an all-white (unlit) display 2. Black-blink cursor (CM10 = 01): Alternately blinks between the normal display and an all-black (all lit) display 3. Black-and-white reversed cursor (CM1-0 = 10): Black-and-white-reversed normal display (no blinking) 4. Black-and-white-reversed blink cursor (CM10 = 11): Alternately blinks between the normal display and a black-and-white-reversed display The above blinking display is switched in a 32-frame unit. In vertical scrolling, note that this window cursor does not automatically move vertically.
HS+1 VS+1 =>
HE+1
HS+1 VS+1 =>
HE+1
VE+1 =>
VE+1 =>
Blink display
Figure 43 White Blink Cursor Display
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HS+1 HE+1 VS+1 => VS+1 =>
HS+1 HE+1
VE+1 =>
VE+1 =>
Blink display
Figure 44 Black Blink Cursor Display
HS+1
HE+1
VS+1 =>
VE+1 =>
Figure 45 Black-and-white Reversed Cursor Display
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HS+1
HE+1
HS+1
HE+1
VS+1 =>
Blink display
VE+1 =>
Figure 46 Black-and-white Reversed Blink Cursor Display
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Vertical Smooth Scroll Display
The HD66750/1 can scroll the graphics display vertically in units of raster-rows. The data storage capacity of the CGRAM is 128 raster-rows. Continuous smooth vertical scrolling is achieved by writing display data into a raster-row area that is not being used for display. After the 128th raster-row is displayed, the first raster-row is displayed again. Using the status read, the user can check the display raster-rows (L6-0) that are currently driving the LCD, and flicker can be eliminated by writing the display data in the CGRAM while the LCD is not driven. Additionally, when display areas of a graphics icon such as a pictogram or a menu bar are partially fixeddisplayed, the remaining areas can be displayed. For details, see the Partial Smooth Scroll Display Function section. Specifically, this function is controlled by incrementing or decrementing the value in the display-start raster-row bits (SL6-0) by 1. For example, to smoothly scroll up, increment display-start raster-row bits (SL6-0) by 1 from 0000000 to 1111111 to scroll 128 raster-rows. Note that the vertical double-height display or window cursor display is not automatically changed in synchronization with the vertical scrolling. When the response speed of the liquid crystal is low or when high-speed scrolling is needed, two- to fourraster-row scrolling is recommended.
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1) Not scrolled SL6 to 0 = 0000000
2) Two raster-rows scrolled up SL6 to 0 = 0000010
3) Four raster-rows scrolled up SL6 to 0 = 0000100
4) Eight raster-rows scrolled up SL6 to 0 = 0001000
Figure 47 Vertical Smooth Scroll
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Partial Smooth Scroll Display Function
The HD66750/1 can partially fixed-display the areas of a graphics icon such as a pictogram or a menu bar, and perform vertical smooth scrolling of the remaining bit-map areas. Since the PS1 to PS0 bits are not used for smooth scrolling of the upper first to 24th display raster-rows but are used for fixed-display, pictograms can be placed on the screen. This function can largely control the rewrite frequencies of the bit-map data during smooth scrolling and reduce the software load of the MPU.
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Table 24 Bit Setting and Display Lines
Bit Set ting COM Position COM1 SL6 to 0 SL6 to 0 SL6 to 0 SL6 to 0 SL6 to 0 SL6 to 0 = 00H
1st r as ter- row 2nd raster-row
SL6 to 0 = 7EH
127th raster-row 128th raster-row 1st raster-row
SL6 to 0 = 7FH
128th raster-row 1st raster-row 2rd raster-row
= 01H
2 nd ras -row ter 3rd raster-r o w 4th raster-row
= 02H
3rd raster-r ow 4th raster-r o w 5th raster-r o w
= 04H
5th raster-row 6th raster-row 7th raster-row
= 07H
8th raster-row 9th raster-row 10th raster-row
= 08H
9thr as ter- row 10th r as ter- row 1 raster-r o 1th w
PS1 to 0 = 00
3rd raste -row r
1 19th raster-r ow
1 20th raster-row 1 21th raster-row
1 21th raster-row 1 22th raster-row
123th raster-row 124th raster-row
126th raster-row 127th raster-row
127t r as h ter- row 128t r as h ter- row
117th raster -row 118th raster -row
118th raster -row 119th raster -row
COM120 COM1
120th raster -row
1st to 8th rast er-rows
1s r as t ter- row 2 raster-row nd 3rd ras -row ter
1st to 8th raster-rows
2 nd raste -row r 3rd raster-r ow 4th raster-row 5th raster-row
1st to 8th rast er-rows
3rd raster-row 4th raster-row 5th raster-row 6th raster-row
1st to 8th raster-rows
5th raster-row 6th raster-row 7th raster-row 8th raster-row
1 st to 8th rast er-rows
8thr as ter- row 9thr as ter- row 1 0t r as h ter- row 11th raster-row
1st to 8th rast er-rows
9th raster-row 10th raster-row 11th ras -row ter 12th raster-row
1st to 8th rast er-rows
127th raster-row 128th raster-row 9th raster-row 10th raster-row
1st to 8th raster-rows
128th raster -row 9th ras -row ter 1 0th ras -row ter 11th raster-r ow
PS1 to 0 = 01
4th ras row ter-
110 th raster-row 1 11th raster-row
1 11th ras -row ter 1 12th raster-row 1 13th raster-row
112th raster -row 113th raster -row 1 th raster-row 14
114th raster-row 115th raster-row 116th raster-row
117th raster-row 118th raster-row 119th raster-row
118th r as ter- row 119th r as ter- row 120th raster-row
116th r as ter- row 117th r as ter- row 118th r as ter- row
1 17th raster-r ow 1 18th raster-r ow 1 19th raster-r ow
COM120 COM1
112 th raster-row
1st to 16t h raster-rows
1st raster-row 2 ra nd ster- row
1st to 16th raster-rows
2 nd ras -row ter 3rd raster-r o w 4th raster-row
1st to 16th rast er-rows
3rd raster-row 4th raster-row 5th raster-row
1st to 16th raster-rows
5th raster-row 6th raster-row 7th raster-row
1 st to 16th rast er-rows
8th raster-row 9th raster-row 10th raster-row
1st to 16th rast er-rows
9th raster-row 10th raster-row 11th ras -row ter
1st to 16th rast er-rows
127th raster-row 128th raster-row 17th raster-row
1st to 16t h raster-rows
128th raster-row 17th raster-row 18th raster-row
PS1 to 0 = 10
3rd raster-row
102th raster-row 103th raster-row
1 03th raster-row 1 04th raster-row 1 05th raster-row
1 04th raster-row 1 05th raster-row 1 06th raster-row
106th raster-row 107th raster-row 108th raster-row
109th raster-row 110th raster -row 11 raster-r ow 1th
110th r as ter- row 11 raster-r ow 1th 112th r as ter- row
116th raster -row 117th raster -row 118th raster -row
117th raster-row 118th raster-row 119th raster-row
COM120 COM1
104th raster-row
1st to 24t h raster-rows
1st to 24th raster-rows
1st to 24th rast er-rows
1st to 24th raster-rows
1 st to 24th rast er-rows
1st to 24th rast er-rows
1st to 24th rast er-rows
1st to 24t h raster-rows
1s r as t ter- row
2nd raster-r ow 3rd raster-row 4th raster-row
3rd r as ter- row 4th raster-r ow 5th raster-r ow
5th raster-row 6th raster-row 7th raster-row
8th raster-row 9th raster-row 10th raster-row
9th raster-r ow 10th r as ter- row 1 raster-r o 1th w
127th raster -row 128th raster -row 2 5th raster -row
128th raster -row 2 5th ras -row ter 2 6th ras -row ter
PS1 to 0 = 11
2 raster-row nd 3rd rast r -row e
94th ras -row ter 95th ras -row ter
95th raster-row 96th raster-row 97th raster-row
96th raster-r ow 97th raster-r ow 98th raster-r ow
98th raster-row 99th raster-row 100th raster-row
101th raster-row 102th raster-row 103th raster-row
102t r as h ter- row 103t r as h ter- row 104t r as h ter- row
116 r as th ter- row 117 r as th ter- row 118 r as th ter- row
1 17th raster-r ow 1 18th raster-r ow 1 19th raster-r ow
COM120 to 0 bits.
96th ras -row ter
Not es: 1. The shadow raster-rows above are fixed-displayed. They do not depend on the setting values of the SL6 2. The SL6 to 0 bits specify the next first scroll display rast er-row of the fixed-displayed rast er-rows.
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Partial Smooth Scroll Display Examples Table 25 Data Setting to the CGRAM CGRAM Address 000 to 07F 080 to 0FF 100 to 17F 180 to 1FF 200 to 27F 280 to 2FF 300 to 37F 380 to 3FF 400 to 47F 480 to 4FF 500 to 57F 580 to 5FF CGRAM Data
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i) Initial Screen Display PS1 to 0 = 01: Fixed-displays the first to eighth raster-rows SL6 to 0 = 0001000: Starts display from the ninth raster-row Fixed display area (1st to 8th raster-rows)
Display-start setting position (9th raster-row)
Scroll area
Figure 48 Example of Initial Screen in the Partial Smooth Scroll Mode
ii) Four-dot Partial Scroll Up PS1 to 0 = 01: Fixed-displays the first to eighth raster-rows SL6 to 0 = 0001100: Starts display from the 13th raster-row Fixed display area (1st to 8th raster-rows)
Display-start setting position (13th raster-row)
Figure 49 Example of Display Screen in the Partial Smooth Scroll Mode (1)
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iii) Eight-dot Partial Scroll Up PS1 to 0 = 01: Fixed-displays the first to eighth raster-rows SL6 to 0 = 0010000: Starts display from the 17th raster-row Fixed display area (1st to 8th raster-rows)
Display-start setting position (17th raster-row)
Figure 50 Example of Display Screen in the Partial Smooth Scroll Mode (2)
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Double-height Display Function
The HD66750/1 can double the height of any desired area in units of raster-rows (dots). The double-height display is done by setting the DHE bit in the display control register to 1. The start position of the double-height display is set by the DS6 to DS0 bits of the double-height display position register, and the double-height display starts at the (the setting value plus one)-th raster-row. The end position is set by the DE6 to DE0 bits of the double-height display position register, and the display ends at the (the setting value plus one)-th raster-row. Here, the end position of the double-height display must be after the start position, so set the register setting values so that DS6-0 DE6-0. When the area specified to be doubled in height is an odd number of raster-rows, the double-height display is done up to the (DE6-0 plus one)-th raster-row. In vertical smooth scrolling, the double-height display position does not automatically move up or down.
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Start doubleheight display (9th raster-row) Double-height display area
End doubleheight display (40th raster-row)
Double-height display on: DHE = 1 Double-height display start: DS6 to 0 = 0001000 Double-height display end: DE6 to 0 = 0010111
Figure 51 Double-height Display (9th to 40th raster-rows)
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Reversed Display Function
The HD66750/1 can display graphics display sections by black-and-white reversal. Black-and-white reversal can be easily displayed when the REV bit in the display control register is set to 1.
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REV = 1 (Reversed display)
Figure 52 Reversed Display
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Partial-display-on Function
The HD66750/1 can program the liquid crystal display drive duty ratio setting (NL3-0 bits), the liquid crystal display drive bias value selection (BS2-0 bits), the boost output level selection (BT1-0 bits), and the contrast adjustment (CT5-0 bits). For example, when the 128 x 120-dot screen is normally displayed with a 1/120 duty ratio, the HD66750/1 can selectively drive only the center of the screen or the top of the screen by combining these register functions and the centering display function (CN bit). This is called partialdisplay-on. Lowering the liquid crystal display drive duty ratio reduces the liquid crystal display drive voltage, thus reducing internal current consumption. This is suitable for a 16 raster-row display (1/16 duty ratio) of a calendar or time in the system-standby state, or the display of only graphics icons (pictograms) at the top of the screen, which enables continuous display with minimal current consumption. The non-displayed lines are constantly driven by the unselected level voltage, thus turning off the LCD for these lines. In general, lowering the liquid crystal display drive duty ratio decreases the optimum liquid crystal display drive voltage and liquid crystal display drive bias value. This reduces output multiplying factors in the booster and greatly controls consumption current. Table 26
Item LCD screen LCD drive position shift LCD drive duty ratio LCD drive bias value (optimum) LCD drive voltage*
Partial-display-on Function (1/120-duty Normal Drive)
Normal Display 128 x 120 dots Not necessary (CN = 0) 1/120 (NL3 to 0 = 1110) 1/11 (BS2 to 0 = 000) 13.5 V to 15.5 V (precisely adjustable using CT5 to 0) Six times (BT1 to 0 = 10) 68 Hz Partial-on Display (Limited to Four-line Display) 128 x 16 dots only on the center of the screen Necessary (CN = 1) 1/16 (NL3 to 0 = 0001) 1/5 (BS2 to 0 = 110) 4 V to 5 V (precisely adjustable using CT5 to 0) Two times (BT1 to 0 = 00) 68 Hz 128 x 16 dots only at the top of the screen Not necessary (CN = 0) 1/16 (NL3 to 0 = 0001) 1/5 (BS2 to 0 = 110) 4 V to 5 V (precisely adjustable using CT5 to 0) Two times (BT1 to 0 = 00) 68 Hz
Boosting output multiplying factor Frame frequency (fosc = 70 kHz)
Note: The LCD drive voltage depends on the LCD materials used. Since the LCD drive voltage is high when the LCD drive duty ratio is high, a low duty ratio enables low-power consumption.
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i) 1/16-duty Drive at the Top of the Screen
1/16-duty drive
Always applying non-selection level
Figure 53 Partial-on Display (Date and Time Indicated) (1)
ii) 1/16-duty Drive at the Center of the Screen (Centering Display)
Always applying nonselection level
1/16-duty drive
Always applying nonselection level
Figure 54 Partial-on Display (Date and Time Indicated) (2)
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Sleep Mode
Setting the sleep mode bit (SLP) to 1 puts the HD66750/1 in the sleep mode, where the device stops all internal display operations, thus reducing current consumption. Specifically, LCD operation is completely halted. Here, all the SEG (SEG1 to SEG128) and COM (COM1 to COM128) pins output the GND level, resulting in no display. If the AP1-0 bits in the power control register are set to 00 in the sleep mode, the LCD drive power supply can be turned off, reducing the total current consumption of the LCD module. Table 27 Comparison of Sleep Mode and Standby Mode
Function LCD control R-C oscillation circuit Sleep Mode (SLP = 1) Turned off Operates normally Standby Mode (STB = 1) Turned off Operation stopped
Standby Mode
Setting the standby mode bit (STB) to 1 puts the HD66750/1 in the standby mode, where the device stops completely, halting all internal operations including the R-C oscillation circuit, thus further reducing current consumption compared to that in the sleep mode. Specifically, all the SEG (SEG1 to SEG128) and COM (COM1 to COM128) pins for the multiplexing drive output the GND level, resulting in no display. If the AP1-0 bits are set to 00 in the standby mode, the LCD drive power supply can be turned off. During the standby mode, no instructions can be accepted other than the start-oscillation instruction. To cancel the standby mode, issue the start-oscillation instruction to stabilize R-C oscillation before setting the STB bit to 0.
Turn off the LCD power supply: AP1 to 0 = 00 Set standby mode: STB = 1
Standby mode
Issue the start-oscillation instruction Wait at least 10 ms Cancel standby mode: STB = 0 Turn on the LCD power supply: AP1 to 0 = 01 / 10 / 11
Figure 55 Procedure for Setting and Canceling Standby Mode
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Absolute Maximum Ratings
Item Power supply voltage (1) Power supply voltage (2) Input voltage Operating temperature Storage temperature Symbol VCC VLCD GND Vt Topr Tstg Unit V V V C C Value 0.3 to +4.6 0.3 to +16.5 0.3 to VCC + 0.3 40 to +85 55 to +110 Notes* 1, 2 1, 3 1 1, 4 1, 5
Notes: 1. If the LSI is used above these absolute maximum ratings, it may become permanently damaged. Using the LSI within the following electrical characteristics limits is strongly recommended for normal operation. If these electrical characteristic conditions are also exceeded, the LSI will malfunction and cause poor reliability. 2. VCC > GND must be maintained. 3. VLCD > GND must be maintained. 4. For bare die and wafer products, specified up to 85uC. 5. This temperature specifications apply to the TCP package.
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DC Characteristics (VCC = 1.8 to 3.6 V, Ta = 40 to +85C*1 )
Item Input high voltage Input low voltage Symbol Min VIH VIL 0.7 VCC 0.3 0.3 Output high voltage (1) VOH1 (DB0-15 pins) Output low voltage (1) (DB0-15 pins) VOL1 Typ N N N Max VCC Unit Test Condition V VCC = 1.8 to 2.4 V VCC = 2.4 to 3.6 V I OH = 0.1 mA VCC = 1.8 to 2.4 V, I OL = 0.1 mA VCC = 2.4 to 3.6 V, I OL = 0.1 mA Id = 0.05 mA, VLCD = 10 V Id = 0.05 mA, VLCD = 10 V Vin = 0 to VCC Notes 2, 3 2, 3 2, 3 2 2 2 4 4 5
0.15 VCC V 0.15 VCC V N 0.2 VCC V V
0.75 VCC N N N N N 3 3 N 50 (T.B.D.) 10
0.15 VCC V 10 10 1 90 (T.B.D.) N k k A A
Driver ON resistance (COM pins) Driver ON resistance (SEG pins) I/O leakage current
RCOM RSEG I Li
N N 1 N
I OP Current consumption during normal operation (VCC GND) Current consumption during sleep mode (VCC GND) Current consumption during standby mode (VCC GND) I SL
6, 7 R-C oscillation, VCC = 3 V, Ta = 25 C, f OSC = 70 kHz (1/120 duty) R-C oscillation, 6, 7 VCC = 3 V, Ta = 25 C, f OSC = 70 kHz (1/120 duty) VCC = 3 V, Ta = 25C 6, 7
N
A
I ST
N
0.1
5
A
LCD drive power supply I LCD current (VLCD GND) LCD drive voltage (VLCD GND) VLCD
N 5.0
25 (T.B.D.) N
40 (T.B.D.) 15.5
A V
VLCD = 15 V, 1/11 bias, 7 Ta = 25 C, f OSC = 70 kHz 8
Note: For the numbered notes, refer to the Electrical Characteristics Notes section following these tables.
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Booster Characteristics (T. B. D.)
Item Two-times-boost output voltage (VLOUT pin) Five-times-boost output voltage (VLOUT pin) Six-times-boost output voltage (VLOUT pin) Seven-timesboost output voltage (VLOUT pin) Use range of boost output voltages Symbol V UP2 Min 3.9 Typ 4.3 Max 4.4 Unit V Test Condition VCC = Vci = 2.2 V, I O = 30 A, C = 1 F, f OSC = 70 kHz, Ta = 25C VCC = Vci = 2.2 V, I O = 30 A, C = 1 F, f OSC = 70 kHz, Ta = 25C VCC = Vci = 2.2 V, I O = 30 A, C = 1 F, f OSC = 70 kHz, Ta = 25C VCC = Vci = 2.2 V, I O = 30 A, C = 1 F, f OSC = 70 kHz, Ta = 25C For two- to seven-times boost Notes 11
V UP5
10.5
10.8
11.0
V
11
V UP6
12.7
12.9
13.2
V
11
V UP7
13.9
15.1
15.4
V
11
V UP2 V UP5 V UP6 V UP7
Vcc
N
15.5
V
11
Note: For the numbered notes, refer to the Electrical Characteristics Notes section following these tables.
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AC Characteristics (VCC = 1.8 to 3.6 V, Ta = 40 to +85C*1 )
Clock Characteristics (V CC = 1.8 to 3.6 V)
Item External clock frequency External clock duty ratio External clock rise time External clock fall time R-C oscillation clock Symbol fcp Duty trcp tfcp f OSC Min 50 45 N N 59 Typ 75 50 N N 74 Max 150 55 0.2 0.2 89 Unit kHz % s s kHz Rf = 390 k, VCC = 3 V Test Condition Notes 9 9 9 9 10
Note: For the numbered notes, refer to the Electrical Characteristics Notes section following these tables.
68-system Bus Interface Timing Characteristics (Vcc = 1.8 to 2.4 V)
Item Enable cycle time Symbol Min Write t CYCE Read t CYCE Enable high-level pulse width Write PWEH Read PWEH Enable low-level pulse width Write PWEL Read PWEL Enable rise/fall time Setup time (RS, R/W to E, CS*) Address hold time Write data setup time Write data hold time Read data delay time Read data hold time t Er, t Ef t ASE t AHE t DSWE t HE t DDRE t DHRE 600 800 120 350 300 300 N 50 20 60 20 N 5 Typ N N N N N N N N N N N N N Max N N N N N N 25 N N N N 300 N ns ns ns ns ns ns ns Figure 62 Figure 62 Figure 62 Figure 62 Figure 62 Figure 62 Figure 62 ns Figure 62 ns Figure 62 Unit ns Test Condition Figure 62
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(Vcc = 2.4 to 3.6 V)
Item Enable cycle time Symbol Min Write t CYCE Read t CYCE Enable high-level pulse width Write PWEH Read PWEH Enable low-level pulse width Write PWEL Read PWEL Enable rise/fall time Setup time (RS, R/W to E, CS*) Address hold time Write data setup time Write data hold time Read data delay time Read data hold time t Er, t Ef t ASE t AHE t DSWE t HE t DDRE t DHRE 380 500 70 250 150 150 N 50 20 60 20 N 5 Typ N N N N N N N N N N N N N Max N N N N N N 25 N N N N 200 N ns ns ns ns ns ns ns Figure 62 Figure 62 Figure 62 Figure 62 Figure 62 Figure 62 Figure 62 ns Figure 62 ns Figure 62 Unit ns Test Condition Figure 62
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80-system Bus Interface Timing Characteristics (Vcc = 1.8 to 2.4 V)
Item Bus cycle time Symbol Min Write t CYCW Read t CYCR Write low-level pulse width Read low-level pulse width Write high-level pulse width Read high-level pulse width Write/Read rise/fall time Setup time (RS to CS*, WR*, RD*) Address hold time Write data setup time Write data hold time Read data delay time Read data hold time PWLW PWLR PWHW PWHR 600 800 120 350 300 300 Typ N N N N N N N N N N N N N Max N N N N N N 25 N N N N 300 N Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Test Condition Figure 63 Figure 63 Figure 63 Figure 63 Figure 63 Figure 63 Figure 63 Figure 63 Figure 63 Figure 63 Figure 63 Figure 63 Figure 63
t WRr , WRf N t AS t AH t DSW tH t DDR t DHR 50 20 60 20 N 5
(Vcc = 2.4 to 3.6 V)
Item Bus cycle time Symbol Min Write t CYCW Read t CYCR Write low-level pulse width Read low-level pulse width Write high-level pulse width Read high-level pulse width Write/Read rise/fall time Setup time (RS to CS*, WR*, RD*) Address hold time Write data setup time Write data hold time Read data delay time Read data hold time PWLW PWLR PWHW PWHR t WRr, WRf t AS t AH t DSW tH t DDR t DHR 380 500 70 250 150 150 N 50 20 60 20 N 5 Typ N N N N N N N N N N N N N Max N N N N N N 25 N N N N 200 N Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Test Condition Figure 63 Figure 63 Figure 63 Figure 63 Figure 63 Figure 63 Figure 63 Figure 63 Figure 63 Figure 63 Figure 63 Figure 63 Figure 63
Reset Timing Characteristics (V CC = 1.8 to 3.6 V)
Item Reset low-level width Symbol t RES Min 1 Typ N Max N Unit ms Test Condition Figure 64
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Electrical Characteristics Notes
1. For bare die products, specified up to 85uC. 2. The following three circuits are I/O pin configurations (figure 56).
Pins: RESET*, CS*, E/WR, RW/RD, RS, OSC1, OPOFF, IM1/0, TEST Vcc PMOS NMOS Vcc PMOS NMOS Pin: OSC2
GND
GND
Pins: DB15 to DB0
Vcc PMOS (Input circuit) NMOS Vcc PMOS (Tri-state output circuit) Output enable Output data
PMOS
NMOS
GND
Figure 56 I/O Pin Configuration
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3. The TEST pin must be grounded and the IM1/0 and OPOFF pins must be grounded or connected to Vcc. 4. Applies to the resistor value (RCOM) between power supply pins V1OUT, V2OUT, V5OUT, GND and common signal pins, and resistor value (RSEG) between power supply pins V1OUT, V3OUT, V4OUT, GND and segment signal pins. 5. This excludes the current flowing through output drive MOSs. 6. This excludes the current flowing through the input/output units. The input level must be fixed high or low because through current increases if the CMOS input is left floating. 7. The following shows the relationship between the operation frequency (fosc) and current consumption (Icc) (figure 57).
Vcc = 3V Vcc = 3 V, fosc = 70 kHz
60 Display on (typ.) 40 Iop (A) 20 Standby (typ.) 0 0 20 40 60 80 100 R-C oscillation frequencies: fosc (kHz) Sleep (typ.)
30 typ. 20 ILCD (A) 10 0 11.0 13.0 15.0 17.0 LCD drive voltage: VLCD (V)
Figure 57 Relationship between the Operation Frequency and Current Consumption 8. Each COM and SEG output voltage is within 0.15 V of the LCD voltage (Vcc, V1, V2, V3, V4, V5) when there is no load. 9. Applies to the external clock input (figure 58).
Th 2 k Oscillator Open OSC1 OSC2 0.7Vcc 0.5Vcc 0.3Vcc t rcp tfcp Duty = Th Th + Tl x 100% Tl
Figure 58 External Clock Supply
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10. Applies to the internal oscillator operations using external oscillation resistor Rf (figure 59 and table 28).
OSC1 Rf OSC2 Since the oscillation frequency varies depending on the OSC1 and OSC2 pin capacitance, the wiring length to these pins should be minimized.
Figure 59 Table 28
External Resistance (Rf) 200 k 270 k 300 k 330 k 360 k 390 k 430 k 470 k
Internal Oscillation
External Resistance Value and R-C Oscillation Frequency (Referential Data)
R-C Oscillation Frequency: fosc Vcc = 1.8 V 86 kHz 70 kHz 64 kHz 60 kHz 57 kHz 54 kHz 49 kHz 46 kHz Vcc = 2.2 V 111 kHz 86 kHz 79 kHz 74 kHz 69 kHz 64 kHz 59 kHz 54 kHz Vcc = 3.0 V 130 kHz 100 kHz 92 kHz 86 kHz 79 kHz 74 kHz 67 kHz 61 kHz Vcc = 4.0 V 140 kHz 108 kHz 98 kHz 91 kHz 84 kHz 78 kHz 71 kHz 65 kHz
11. Booster characteristics test circuits are shown in figure 60.
(Five to seven times b oosting
V cc
V ci C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5C6+ C6V LOUT V LCD
+ + + + + +
1 F 1 F 1 F 1 F 1 F 1 F
GND
+
1 F
Figure 60
Booster
90
HD66750/1
Referential data VUP6 = VLCD - GND, VUP7 = VLCD - GND (i) Relation between the obtained voltage and input voltage Six-times boosting 18.0 15.0 VUP6 (V) 12.0 9.0 1.5 typ. 18.0 VUP7 (V) 13.0 8.0 1.5 2.0 2.5 Vci (V) Vci = Vcc, fosc = 70 kHz, Ta = 25C, DC1 to 0 = 00 3.0 Seven-times boosting typ.
2.0
2.5 Vci (V)
3.0
Vci = Vcc, fosc = 70 kHz, Ta = 25C, DC1 to 0= 00 (ii) Relation between the obtained voltage and temperature Six-times boosting 17.0 typ. 15.0 VUP6 (V) 13.0 11.0
Seven-times boosting
18.0 VUP7 (V) 16.0 14.0
typ.
-60
-20
0 20
60
100
-60
-20 0
20 Ta (C)
60
100
Ta (C) Vci = Vcc = 2.4 V, fosc = 70 kHz, Io = 30 A, DC1 to 0= 00 (iii) Relation between the obtained voltage and capacity 16.0 15.0 VUP6 (V) 14.0 13.0 11.0 Six-times boosting
Vci = Vcc = 2.4 V, fosc = 70 kHz, Io = 30 A, DC1 to 0 = 00
Seven-times boosting 18.0 typ. 17.0 VUP7 (V) 16.0 15.0
typ.
0.5
1.0 C (F)
1.5
14.0
0.5
1.0 C (F)
1.5
Vci = Vcc = 2.4 V, fosc = 70 kHz, Io = 30 A, DC1 to 0 = 00
Vci = Vcc = 2.4 V, fosc = 70 kHz, Io = 30 A, DC1 to 0 = 00
Figure 60 Booster (cont)
91
HD66750/1
(iv) Relation between the obtained voltage and current Six-times boosting 15.0 14.5 VUP6 (V) 14.0 13.5 13.0 0 50 100 Io (A) Vci = Vcc = 2.4 V, fosc = 70 kHz, Ta = 25C, DC1 to 0 = 00 150 200 VUP7 (V) 17.5 17.0 16.5 16.0 15.5 0 50 100 Io (A) Vci = Vcc = 2.4 V, fosc = 70 kHz, Ta = 25C, DC1 to 0 = 00 150 200 Seven-times boosting
Figure 60 Booster (cont)
Load Circuits
AC Characteristics Test Load Circuits
Data bus: DB15 to DB0 Test Point
50 pF
Figure 61 Load Circuit
92
HD66750/1
Timing Characteristics
68-system Bus Operation
RS R/W
VIH VIL
VIH VIL
tASE CS*
VIL
tAHE
VIL
PWEH E
VIH VIL
*1
PWEL
VIL VIL
VIH
tEr
tEf tDSWE
tCYCE tHE
VIH VIL
DB0 to DB15 tDDRE DB0 to DB15
VIH VIL
Write data
tDHRE
VOH1 VOL1
Read data
VOH1 VOL1
Note 1: PWEH is specified in the overlapped period when CS* is low and E is high.
Figure 62 68-system Bus Timing
93
HD66750/1
80-system Bus Operation
RS
VIH VIL
VIH VIL
tAS CS*
VIH VIL PWLW, PWLR
*1
tAH
PWHW PWHR VIH
WR* RD*
VIH VIL
VIH VIL
tWRr tCYCW, tCYCR tDSW
tWRf tHWR
VIH VIL
DB0 to DB15 tDDR DB0 to DB15
VIH VIL
Write data
tDHR
VOH1 VOL1
Read data
VOH1 VOL1
Note 1: PWLW and PWLR are s pecified in the overlapped period when CS* is low and W R* or RD* is low.
Figure 63 80-system Bus Timing Reset Operation
tRES RESET*
VIL
VIL
Figure 64 Reset Timing
94
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All right reserved: No one is permitted to reproduce or duplicated, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party of Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.

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